公开(公告)号：US20070102735A1

公开(公告)日：2007-05-10

申请号：US11537865

申请日：2006-10-02

申请人： Kei KANEMOTO ,  Hideaki OKA

发明人： Kei KANEMOTO ,  Hideaki OKA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device includes: a semiconductor substrate; a well formed on the semiconductor substrate; a semiconductor layer formed by epitaxial growth avoiding the well; a buried insulating layer embedded between the semiconductor substrate and the semiconductor layer; a first gate electrode formed on the semiconductor layer, the first gate electrode having a first side and a second side; a first source layer and a first drain layer formed on the semiconductor layer, the first source layer being arranged on the first side of the first gate electrode and the first drain layer being arranged on the second side of the first gate electrode; a second gate electrode formed on the well, the second gate electrode having a third side and a fourth side; and a second source layer and a second drain layer formed on the well, the second source layer being arranged on the third side of the second gate electrode and the second drain layer being arranged on the fourth side of the second gate electrode.

摘要翻译： 半导体器件包括：半导体衬底; 在半导体衬底上形成的阱; 通过避免井的外延生长形成的半导体层; 嵌入在所述半导体衬底和所述半导体层之间的掩埋绝缘层; 形成在所述半导体层上的第一栅电极，所述第一栅电极具有第一侧和第二侧; 形成在所述半导体层上的第一源极层和第一漏极层，所述第一源极层布置在所述第一栅电极的第一侧上，所述第一漏极层布置在所述第一栅电极的第二侧上; 形成在所述阱上的第二栅电极，所述第二栅电极具有第三侧和第四侧; 以及形成在所述阱上的第二源极层和第二漏极层，所述第二源极层布置在所述第二栅电极的第三侧上，所述第二漏极层布置在所述第二栅电极的第四侧上。

公开(公告)号：US06235563B1

公开(公告)日：2001-05-22

申请号：US07790107

申请日：1991-11-07

申请人： Hideaki Oka ,  Satoshi Takenaka ,  Masafumi Kunii

发明人： Hideaki Oka ,  Satoshi Takenaka ,  Masafumi Kunii

IPC分类号： H01L2132

CPC分类号： H01L21/02667 ,  H01L21/2022 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

摘要： An improved polycrystalline or polysilicon film having large grain size, such as 1 &mgr;m to 2 &mgr;m in diameter or greater, is obtained over the methods of the prior art by initially forming a silicon film, which may be comprised of amorphous silicon or micro-crystalline silicon or contains micro-crystal regions in the amorphous phase, at a low temperature via a chemical vapor deposition (CVD) method, such as by plasma chemical vapor deposition (PCVD) with silane gas diluted with, for example, hydrogen, argon or helium at a temperature, for example, in the range of room temperature to 600° C. This is followed by solid phase recrystallization of the film to form a polycrystalline film which is conducted at a relatively low temperature in the range of about 550° C. to 650° C. in an inert atmosphere, e.g., N or Ar, for a period of about several hours to 40 or more hours wherein the temperature is gradually increased, e.g., at a temperature rise rate below 20° C./min, preferably about 5° C./min, to a prescribed recrystallization temperature within the range about 550° C. to 650° C. Further, between the step of film formation and the step of solid phase recrystallization, the film may be thermally treated at a relatively low temperature, e.g., over 300° C. and preferably between approximately 400° C. to 500° C. for a period of several minutes, such as 30 minutes, to remove hydrogen from the film prior to solid phase recrystallization.

摘要翻译： 通过最初形成可以由非晶硅或微晶体构成的硅膜，通过现有技术的方法获得具有大晶粒尺寸的改善的多晶或多晶硅膜，例如1μm至2μm直径或更大的晶粒 硅或通过化学气相沉积（CVD）方法在低温下包含非晶相中的微晶区域，例如通过用例如氢，氩或氦稀释的硅烷气体的等离子体化学气相沉积（PCVD） 在例如室温至600℃的温度下进行，然后进行固相重结晶，形成多晶膜，该多晶膜在约550℃的较低温度下进行。 在惰性气氛（例如N或Ar）中，在温度逐渐升高的情况下，例如在升温速度低于20℃/分钟的情况下，在约数小时至40小时的时间内， 优选约5° 在约550℃至650℃的范围内的规定的再结晶温度。此外，在成膜步骤和固相重结晶步骤之间，可以在相对低的温度下热处理 ，例如超过300℃，优选在约400℃至500℃之间，持续几分钟，例如30分钟，以在固相重结晶之前从膜中除去氢。

公开(公告)号：US20070176236A1

公开(公告)日：2007-08-02

申请号：US11649170

申请日：2007-01-03

申请人： Hideaki Oka ,  Kei Kanemoto

发明人： Hideaki Oka ,  Kei Kanemoto

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor device includes a semiconductor layer formed by epitaxial growth in a first region which is obtained by etching a semiconductor substrate to a predetermined depth, a surface of the semiconductor layer having a same height from the bottom of the semiconductor substrate as a height of a surface of the semiconductor substrate, a buried insulating layer buried between the semiconductor substrate and the semiconductor layer and an element isolation region separating each element region in the semiconductor layer and isolating the semiconductor layer from the semiconductor substrate in plan.

摘要翻译： 半导体器件包括通过在通过将半导体衬底蚀刻到预定深度而获得的第一区域中外延生长形成的半导体层，半导体层的与半导体衬底的底部相同高度的表面作为半导体衬底的高度 半导体衬底的表面，埋在半导体衬底和半导体层之间的掩埋绝缘层，以及分隔半导体层中的每个元件区域并将半导体层与半导体衬底隔离的元件隔离区域。

公开(公告)号：US20070018246A1

公开(公告)日：2007-01-25

申请号：US11447926

申请日：2006-06-07

申请人： Juri Kato ,  Hideaki Oka ,  Kei Kanemoto ,  Toshiki Hara ,  Tetsushi Sakai

发明人： Juri Kato ,  Hideaki Oka ,  Kei Kanemoto ,  Toshiki Hara ,  Tetsushi Sakai

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer, a second insulating layer formed on the first single-crystal semiconductor layer, a second single-crystal semiconductor layer formed on the second insulating layer and having a film thickness smaller than a film thickness of the first single-crystal semiconductor layer, a gate electrode formed on the second single-crystal semiconductor layer, and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.

摘要翻译： 半导体器件包括由形成在第一绝缘层上的第一单晶半导体层，形成在第一单晶半导体层上的第二绝缘层构成的背栅电极，形成在第二绝缘层上的第二单晶半导体层 并且具有比第一单晶半导体层的膜厚小的膜厚度，形成在第二单晶半导体层上的栅极电极以及形成在第二单晶半导体层上的源极和漏极层，以及 布置在栅电极的相应侧上。

公开(公告)号：US07666795B2

公开(公告)日：2010-02-23

申请号：US11955700

申请日：2007-12-13

申请人： Juri Kato ,  Hideaki Oka ,  Masamitsu Uehara

发明人： Juri Kato ,  Hideaki Oka ,  Masamitsu Uehara

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3141 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/823481 ,  H01L21/84

摘要： A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern.

摘要翻译： 一种制造半导体器件的方法包括在Si衬底上形成SiGe层，形成虚拟图案以暴露Si衬底的表面，并在蚀刻剂与虚拟图案接触的同时湿蚀刻SiGe层。

公开(公告)号：US07009029B2

公开(公告)日：2006-03-07

申请号：US10464474

申请日：2003-06-19

申请人： Hideaki Oka ,  Hideharu Matsuoka ,  Toru Kuki

发明人： Hideaki Oka ,  Hideharu Matsuoka ,  Toru Kuki

IPC分类号： C08G69/26 ,  C08K3/00 ,  C08L77/00 ,  C08L3/22

CPC分类号： C08K3/22 ,  C08K2003/2241 ,  C08L77/00

摘要： Provided is a polyamide composition comprising 100 parts by weight of (A) a polyamide having dicarboxylic acid units containing 60 to 100 mol % of terephthalic acid units, and diamine units containing 60 to 100 mol % of 1,9-nonanediamine units and/or 2-methyl-1,8-octanediamine units, and 5 to 100 parts by weight of (B) a titanium oxide with an average particle size of 0.1 to 0.5 μm. The polyamide composition shows excellent heat resistance enough to withstand the SMT process, and gives a molded article with excellent whiteness and surface-reflectance.

摘要翻译： 本发明提供一种聚酰胺组合物，其包含100重量份的（A）具有含有60〜100摩尔％的对苯二甲酸单元的二羧酸单元的聚酰胺和含有60〜100摩尔％的1,9-壬二胺单元的二胺单元和/或 2-甲基-1,8-辛二胺单元和5〜100重量份的（B）平均粒径为0.1〜0.5μm的氧化钛。 聚酰胺组合物显示出优异的耐热性，足以承受SMT工艺，并且得到具有优异的白度和表面反射率的模塑制品。

公开(公告)号：US06258927B1

公开(公告)日：2001-07-10

申请号：US09494046

申请日：2000-01-31

申请人： Hideaki Oka ,  Toru Kuki ,  Kozo Tamura

发明人： Hideaki Oka ,  Toru Kuki ,  Kozo Tamura

IPC分类号： C08L7700

CPC分类号： C08K3/38 ,  C08K3/24 ,  C08K5/03 ,  H05K1/0346 ,  H05K1/0373 ,  C08L77/00

摘要： A polyamide composition, comprising: (A) 100 parts by weight of a polyamide, (B) from 10 to 200 parts by weight of an aromatic ring-containing bromine compound, and (C) from 0.1 to 100 parts by weight of at least one flame-retardant synergist selected from metal salts of stannic acid and alkaline earth metal salts of boric acid. The polyamide composition has good flame retardancy and heat resistance, and exhibits good thermal stability and continuous moldability when molded in melt, and it can be molded into good moldings having excellent appearances, especially fine color tone, without giving much gas.

摘要翻译： 一种聚酰胺组合物，其包含：（A）100重量份的聚酰胺，（B）10〜200重量份的含芳环的溴化合物，和（C）0.1〜100重量份的至少 一种选自硼酸的锡酸和碱土金属盐的金属盐的阻燃增效剂。 聚酰胺组合物具有良好的阻燃性和耐热性，并且在熔融成型时表现出良好的热稳定性和连续的成型性，并且可以模塑成具有优异外观的特别良好的模制品，特别是细色调，而不产生大量气体。

公开(公告)号：US3947504A

公开(公告)日：1976-03-30

申请号：US446421

申请日：1974-02-27

申请人： Sunao Kyo ,  Hideaki Oka ,  Katsuhiko Hayashi ,  Hidetsugu Tanaka

发明人： Sunao Kyo ,  Hideaki Oka ,  Katsuhiko Hayashi ,  Hidetsugu Tanaka

IPC分类号： C07C1/247 ,  C07C20060101 ,  C07C1/00 ,  C07C7/04 ,  C07C11/18 ,  C07C27/00 ,  C07C27/26 ,  C07C29/80 ,  C07C33/02 ,  C07C33/025 ,  C07C67/00 ,  C07D309/18 ,  C07D319/06 ,  C07D323/06 ,  C07C29/24

CPC分类号： C07C29/92

摘要： The 3-methyl-3-butene-1-ol contained in the oily mixture obtained in the production of isoprene by the reaction of isobutene and formaldehyde through the intermediate 4,4-dimethyl-1,3-dioxane can be isolated by adding boric acid to said mixture to form the boric acid ester of 3-methyl-3-butene-1-ol and recovering the higher boiling fraction having a boiling point of above 160.degree.C.

摘要翻译： 通过异丁烯和甲醛通过中间体4,4-二甲基-1,3-二恶烷的反应制备异戊二烯得到的油状混合物中所含的3-甲基-3-丁烯-1-醇可以通过加入硼酸 酸与所述混合物反应以形成3-甲基-3-丁烯-1-醇的硼酸酯，并回收沸点高于160℃的较高沸点馏分。

公开(公告)号：US07495287B2

公开(公告)日：2009-02-24

申请号：US11649170

申请日：2007-01-03

申请人： Hideaki Oka ,  Kei Kanemoto

发明人： Hideaki Oka ,  Kei Kanemoto

IPC分类号： H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor device includes a semiconductor layer formed by epitaxial growth in a first region which is obtained by etching a semiconductor substrate to a predetermined depth, a surface of the semiconductor layer having a same height from the bottom of the semiconductor substrate as a height of a surface of the semiconductor substrate, a buried insulating layer buried between the semiconductor substrate and the semiconductor layer and an element isolation region separating each element region in the semiconductor layer and isolating the semiconductor layer from the semiconductor substrate in plan.

摘要翻译： 半导体器件包括通过在通过将半导体衬底蚀刻到预定深度而获得的第一区域中外延生长形成的半导体层，半导体层的与半导体衬底的底部相同高度的表面作为半导体衬底的高度 半导体衬底的表面，埋在半导体衬底和半导体层之间的掩埋绝缘层，以及分隔半导体层中的每个元件区域并将半导体层与半导体衬底隔离的元件隔离区域。

公开(公告)号：US20070075317A1

公开(公告)日：2007-04-05

申请号：US11489572

申请日：2006-07-20

申请人： Juri Kato ,  Hideaki Oka ,  Kei Kanemoto ,  Toshiki Hara ,  Tetsushi Sakai

发明人： Juri Kato ,  Hideaki Oka ,  Kei Kanemoto ,  Toshiki Hara ,  Tetsushi Sakai

IPC分类号： H01L29/04

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer; a second insulating layer formed on the first single-crystal semiconductor layer and having a film thickness smaller than a film thickness of the first insulating layer; a second single-crystal semiconductor layer formed on the second insulating layer; a gate electrode formed on the second single-crystal semiconductor layer; and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.

摘要翻译： 半导体器件包括由形成在第一绝缘层上的第一单晶半导体层构成的背栅电极; 形成在所述第一单晶半导体层上并具有比所述第一绝缘层的膜厚小的膜厚度的第二绝缘层; 形成在所述第二绝缘层上的第二单晶半导体层; 形成在第二单晶半导体层上的栅电极; 以及形成在第二单晶半导体层上并且布置在栅电极的相应侧上的源极和漏极层。