公开(公告)号：US06774641B2

公开(公告)日：2004-08-10

申请号：US10173007

申请日：2002-06-18

申请人： Hideki Sasaki ,  Takahiro Yaguchi ,  Akira Wakui ,  Seishi Eya ,  Takashi Harada ,  Toshihide Kuriyama

发明人： Hideki Sasaki ,  Takahiro Yaguchi ,  Akira Wakui ,  Seishi Eya ,  Takashi Harada ,  Toshihide Kuriyama

IPC分类号： G01R2728

CPC分类号： G06F17/5036

摘要： In a printed circuit board design support apparatus for supporting design of a printed circuit board by calculating a radiation amount of electromagnetic radiation caused by an interconnection on the basis of design information related to each of the printed circuit board having a ground plane, interconnections formed on the printed circuit board, and components to be mounted on the printed circuit board, an arithmetic unit calculates a common mode (CM) radiation amount of the interconnection on the basis of a CM radiation amount ratio that indicates a ratio of a common mode (CM) radiation amount of electromagnetic radiation caused by the ground plane in correspondence with the interconnection to a differential mode (DM) radiation amount of electromagnetic radiation caused by the interconnection. A printed circuit board design support method and program are also disclosed.

摘要翻译： 在印刷电路板设计支持装置中，用于通过基于与具有接地平面的印刷电路板相关的设计信息计算由互连引起的电磁辐射的辐射量来支持印刷电路板的设计，在 印刷电路板和要安装在印刷电路板上的部件，运算单元基于指示共模（CM）的比率的CM辐射量比率来计算互连的共模（CM）辐射量 ）由与互连造成的电磁辐射辐射量对应于由互连造成的电磁辐射的差分模式（DM）辐射量的对应。 还公开了印刷电路板设计支持方法和程序。

公开(公告)号：US20060161874A1

公开(公告)日：2006-07-20

申请号：US10561195

申请日：2004-06-16

申请人： Takashi Harada ,  Takahiro Yaguchi ,  Akira Wakui ,  Seishi Eya ,  Shunsuke Fujimoto

发明人： Takashi Harada ,  Takahiro Yaguchi ,  Akira Wakui ,  Seishi Eya ,  Shunsuke Fujimoto

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5068 ,  H05K1/0231 ,  H05K3/0005 ,  H05K2201/09309

摘要： A printed circuit wiring board designing support device includes a layout data receiving section receiving printed circuit board layout data through an input/output section, a section for extracting structures of power supply/ground planes, a via hole extracting section for extracting a via hole interconnecting the wirings extending over power supply/ground planes, a capacitor extracting section for extracting a capacitor connected between power supply/ground planes, a distance measuring section for measuring the distance between the via hole and the capacitor, a database where the allowable distance value between the via hole and the capacitor in respect to the distance between the power supply and ground planes is recorded, an examination section for comparing the capacitor/via hole distance with the allowable distance value, and a warning section for issuing a warning when the distance between the via hole and the capacitor is larger than the allowable distance value.

摘要翻译： 一种印刷电路布线板设计支援装置，包括布局数据接收部分，通过输入/输出部分接收印刷电路板布局数据，用于提取电源/接地层结构的部分，通孔提取部分，用于提取互连的通孔 在电源/接地层上延伸的布线，用于提取连接在电源/接地层之间的电容器的电容器提取部分，用于测量通孔和电容器之间的距离的距离测量部分， 记录通孔和电容器相对于电源与接地面之间的距离，用于将电容器/通孔距离与允许距离值进行比较的检查部分和用于在电容器/通孔距离与接地面之间的距离 通孔和电容器大于容许距离值。

公开(公告)号：US07168058B2

公开(公告)日：2007-01-23

申请号：US10561195

申请日：2004-06-16

申请人： Takashi Harada ,  Takahiro Yaguchi ,  Akira Wakui ,  Seishi Eya ,  Shunsuke Fujimoto

发明人： Takashi Harada ,  Takahiro Yaguchi ,  Akira Wakui ,  Seishi Eya ,  Shunsuke Fujimoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H05K1/0231 ,  H05K3/0005 ,  H05K2201/09309

摘要： A printed circuit wiring board designing support device includes a layout data receiving section receiving printed circuit board layout data through an input/output section, a section for extracting structures of power supply/ground planes, a via hole extracting section for extracting a via hole interconnecting the wirings extending over power supply/ground planes, a capacitor extracting section for extracting a capacitor connected between power supply/ground planes, a distance measuring section for measuring the distance between the via hole and the capacitor, a database where the allowable distance value between the via hole and the capacitor in respect to the distance between the power supply and ground planes is recorded, an examination section for comparing the capacitor/via hole distance with the allowable distance value, and a warning section for issuing a warning when the distance between the via hole and the capacitor is larger than the allowable distance value.

摘要翻译： 一种印刷电路布线板设计支援装置，包括布局数据接收部分，通过输入/输出部分接收印刷电路板布局数据，用于提取电源/接地层结构的部分，通孔提取部分，用于提取互连的通孔 在电源/接地层上延伸的布线，用于提取连接在电源/接地层之间的电容器的电容器提取部分，用于测量通孔和电容器之间的距离的距离测量部分， 记录通孔和电容器相对于电源与接地面之间的距离，用于将电容器/通孔距离与可允许距离值进行比较的检查部分和用于当电容器/通孔距离与接地面之间的距离 通孔和电容器大于容许距离值。

公开(公告)号：US06519741B2

公开(公告)日：2003-02-11

申请号：US09764282

申请日：2001-01-19

申请人： Takahiro Yaguchi ,  Kiyoshi Asao ,  Hideki Sasaki ,  Takashi Harada

发明人： Takahiro Yaguchi ,  Kiyoshi Asao ,  Hideki Sasaki ,  Takashi Harada

IPC分类号： G06F1750

CPC分类号： G06F17/5063 ,  H05K1/0231 ,  H05K3/0005

摘要： Disclosed is a power decoupling circuit generating system and method capable of easily generating a power decoupling circuit for each device such as an LSI. On the basis of information regarding parameters of generating a power decoupling circuit held in a capacitor parts library and a line calculation parameter file, a power decoupling circuit of a &pgr;-type low pass filter construction having first and second decoupling capacitors to be added to a power supply terminal of a device as a target from which high frequency noise is prevented from being passed to a power plane and a power line corresponding to an inductance is automatically generated by a power decoupling circuit generating unit, thereby making calculation for generating the power decoupling circuit unnecessary.

摘要翻译： 公开了能够容易地为诸如LSI的每个设备产生功率去耦电路的功率去耦电路产生系统和方法。 基于产生保持在电容器部件库中的电源去耦电路的参数的信息和行计算参数文件，具有第一和第二去耦电容器的π型低通滤波器结构的功率去耦电路被添加到 作为防止高频噪声被传递到电源面的设备的电源端子，并且由电源解耦电路产生单元自动产生与电感相对应的电力线，由此进行用于产生电力去耦的计算 电路不必要

公开(公告)号：US07216327B2

公开(公告)日：2007-05-08

申请号：US10777103

申请日：2004-02-13

申请人： Takahiro Yaguchi ,  Seishi Eya

发明人： Takahiro Yaguchi ,  Seishi Eya

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K3/0005 ,  H05K3/46

摘要： A device for estimating the required number of board layer to provide necessary wiring in a printed circuit board or a LSI package, a system including the device, a method and a program for estimating the same. In this system, positional information of pins mounted to each component and a board, and connection information between pins are retrieved from a pin positional information file and a net list file. Further, information about an order of layers to be added, a diameter of a via in respective layers and obstacles to wiring is retrieved from the net list file an added layer structure defining file. Thereafter, information about a layer structure, vias, an area where wiring is prohibited is stored in a storage. A wiring route searching section determines whether or not it is possible to form necessary wiring under the present structure. When the wiring route searching section determines it to be impossible, a layer in the next order is added according to information about added layers. Subsequently, the wiring route searching section judges the possibility again. When determining it to be possible, the wiring route searching section outputs the present layer structure to an output device. By this means, it becomes possible to estimate a layer structure and the number of layers.

摘要翻译： 一种用于估计所需数量的电路板层以在印刷电路板或LSI封装中提供必要布线的装置，包括该装置的系统，方法和用于估计该装置的程序。 在该系统中，从引脚位置信息文件和网络列表文件检索安装到每个部件和板上的引脚的位置信息以及引脚之间的连接信息。 此外，从网络列表文件检索关于要添加的层的顺序，各层中的通孔的直径和布线的障碍的信息，添加层结构定义文件。 此后，存储有关层结构，通孔，禁止布线的区域的信息。 布线路径搜索部确定在本结构下是否可能形成必要的布线。 当布线路径搜索部确定为不可能时，根据关于添加的层的信息，添加下一顺序的层。 随后，布线路径搜索部分再次判断可能性。 当确定可能时，布线路径搜索部分将当前层结构输出到输出装置。 通过这种方式，可以估计层结构和层数。

公开(公告)号：US20050278679A1

公开(公告)日：2005-12-15

申请号：US10777103

申请日：2004-02-13

申请人： Takahiro Yaguchi ,  Seishi Eya

发明人： Takahiro Yaguchi ,  Seishi Eya

IPC分类号： G06F17/50 ,  H01L23/12 ,  H03K17/693 ,  H05K1/00 ,  H05K3/00 ,  H05K3/46

CPC分类号： G06F17/5077 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K3/0005 ,  H05K3/46

摘要： A device for estimating the required number of board layer to provide necessary wiring in a printed circuit board or a LSI package, a system including the device, a method and a program for estimating the same. In this system, positional information of pins mounted to each component and a board, and connection information between pins are retrieved from a pin positional information file and a net list file. Further, information about an order of layers to be added, a diameter of a via in respective layers and obstacles to wiring is retrieved from the net list file an added layer structure defining file. Thereafter, information about a layer structure, vias, an area where wiring is prohibited is stored in a storage. A wiring route searching section determines whether or not it is possible to form necessary wiring under the present structure. When the wiring route searching section determines it to be impossible, a layer in the next order is added according to information about added layers. Subsequently, the wiring route searching section judges the possibility again. When determining it to be possible, the wiring route searching section outputs the present layer structure to an output device. By this means, it becomes possible to estimate a layer structure and the number of layers.

摘要翻译： 一种用于估计所需数量的电路板层以在印刷电路板或LSI封装中提供必要布线的装置，包括该装置的系统，方法和用于估计该装置的程序。 在该系统中，从引脚位置信息文件和网络列表文件检索安装到每个部件和板上的引脚的位置信息以及引脚之间的连接信息。 此外，从网络列表文件检索关于要添加的层的顺序，各层中的通孔的直径和布线的障碍的信息，添加层结构定义文件。 此后，存储有关层结构，通孔，禁止布线的区域的信息。 布线路径搜索部确定在本结构下是否可能形成必要的布线。 当布线路径搜索部确定为不可能时，根据关于添加的层的信息，添加下一顺序的层。 随后，布线路径搜索部分再次判断可能性。 当确定可能时，布线路径搜索部分将当前层结构输出到输出装置。 通过这种方式，可以估计层结构和层数。

公开(公告)号：US08516431B2

公开(公告)日：2013-08-20

申请号：US12764481

申请日：2010-04-21

申请人： Takahiro Yaguchi

发明人： Takahiro Yaguchi

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F2217/84

摘要： A design rule check system includes: a design rule check unit that performs a design rule checks on wiring information which indicates a wiring pattern of a net on the basis of a design rule which includes a constraint condition of a wiring pattern; and a screening processing unit which generates information about an error for each clock frequency of each net based on a result of the design rule check and outputs the information to an indicating device.

摘要翻译： 设计规则检查系统包括：设计规则检查单元，其基于包括布线图案的约束条件的设计规则，对指示网络的布线图案的布线信息执行设计规则检查; 以及筛选处理单元，其基于设计规则检查的结果生成关于每个网络的每个时钟频率的错误的信息，并将该信息输出到指示装置。

公开(公告)号：US07356790B2

公开(公告)日：2008-04-08

申请号：US11169584

申请日：2005-06-30

申请人： Yoshiaki Maruyama ,  Takahiro Yaguchi

发明人： Yoshiaki Maruyama ,  Takahiro Yaguchi

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： To estimate the number of layers required for drawing wirings out of a BGA component at a high speed. A layer number estimation device includes: a bottleneck line detection means, a wiring layer adding means, and a repeating means. The bottleneck line detection means detects a line as a bottleneck line, among a plurality of lines formed by connecting electrodes, where the number of electrodes located nearer the center side than the lines is greater comparing with the number of wirings capable of passing through the lines. The wiring layer adding means disposes electrodes, among the electrodes located nearer the center side than the bottleneck line, which remain after subtracting the number of wirings capable of passing through the bottleneck line, on the next wiring layer with vias. The repeating means causes the bottleneck line detection means and the wiring layer adding means to be executed to the next wiring layer.

摘要翻译： 估计从BGA组件中高速绘制布线所需的层数。 层数估计装置包括：瓶颈线检测装置，布线层添加装置和重复装置。 瓶颈线检测装置在连接电极形成的多个线之间检测线作为瓶颈线，其中位于比线更靠中心侧的电极数量比能够通过线路的布线数量更大 。 在下一个具有通孔的布线层上，布线层添加装置将电极放置在比瓶颈线更靠近中心侧的电极中，该电极在减去能够穿过瓶颈线的布线数之后保留。 重复装置使得瓶颈线检测装置和布线层添加装置被执行到下一个布线层。

公开(公告)号：US5537008A

公开(公告)日：1996-07-16

申请号：US266598

申请日：1994-06-28

申请人： Osamu Matsuda ,  Takahiro Yaguchi

发明人： Osamu Matsuda ,  Takahiro Yaguchi

IPC分类号： H01K1/32 ,  H01K1/50 ,  H05B37/00

CPC分类号： H01K1/50

摘要： An incandescent lamp which is operable at about 200-275 V is obtainable by enclosing a filling composition consisting of about 80-95% by volume of krypton gas and about 5-20% by volume of nitrogen gas in a glass envelope bearing a tungsten filament and an inner volume of about 0.2-1.2 ml/operating wattage in an amount of about 0.7-0.9 ml/ml of the inner volume. The incandescent lamp exhibits satisfactory luminous characteristics and an extended life expectancy without causing arc discharge even when operated at a voltage of about 200-275 V. Thus a lighting device which comprises such an incandescent lamp as the luminous source and a power source capable of energizing it at a voltage of about 200-275 V is very useful in general and special illumination.

摘要翻译： 可在约200-275V下操作的白炽灯可以通过将包含约80-95体积％的氪气和约5-20体积％氮气的填充组合物包含在具有钨丝的玻璃封套中来获得 内容积为约0.2-1.2ml /操作功率，其量为内容积的约0.7-0.9ml / ml。 白炽灯即使在约200-275V的电压下操作，也能够发出令人满意的发光特性和延长的使用寿命，而不产生电弧放电。因此，一种照明装置，其包括作为发光源的白炽灯和能够发光的电源 它在约200-275V的电压下是非常有用的一般和特殊的照明。

公开(公告)号：US07114132B2

公开(公告)日：2006-09-26

申请号：US10125350

申请日：2002-04-19

申请人： Takahiro Yaguchi

发明人： Takahiro Yaguchi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： There is provided a circuit design supporting device, a circuit board design supporting system, a circuit board design supporting server, a circuit board design supporting client, a circuit design supporting method, and a program for realizing the device for designing a layout of main components such as LSI, etc. on a circuit board such as a printed circuit board wherein unnecessary electromagnetic radiation is suppressed. The circuit design supporting device comprises a noise generating level adding means and a component locating means. The noise generating level adding means adds noise generating level information to a component to be located on a printed circuit board. The component locating means includes a component position detecting section, a voltage distribution detecting section, a noise generating level comparing section, and an error informing section. The component position detecting section detects a position of the component moved on the printed circuit board. The voltage distribution detecting section detects a voltage level on the printed circuit board in the detected position of the component. The noise generating level comparing section compares the detected voltage level with the noise generating level added to the component. The error informing section informs a user of an error when the voltage level on the printed circuit board is equal to or larger than the noise generating level as a result of the comparison.