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公开(公告)号：US07966360B2
公开(公告)日：2011-06-21
申请号：US11833030
申请日：2007-08-02
申请人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto
发明人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto
IPC分类号： G06F17/10
CPC分类号： H03H17/0657 , H03H17/0223 , H03H17/0229 , H03H17/06 , H03H17/0621 , H03H2218/085
摘要： An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.
摘要翻译： A / D转换部分以符号速率M倍的模拟信号执行过采样，以将模拟信号转换为数字信号。 FIR滤波部分具有两个具有多个延迟元件的延迟元件序列。 两个延迟元件序列具有不同的延迟方向，即正向和反向。 可以切换延迟方向，并且根据具有这种延迟元件序列的有限脉冲响应列，进行卷积计算。 相位确定部确定在判定部中作出判定所使用的相位。 决定部分使用在相位确定部分中确定的相位来对滤波信号做出决定以产生位数据。 因此，实现了数字信号接收装置，其在不增加过采样数量的情况下确定高精度的相位，并且在具有减小的电路规模的情况下执行快速计算。
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公开(公告)号：US07577124B2
公开(公告)日：2009-08-18
申请号：US10942122
申请日：2004-09-16
IPC分类号： H04Q7/24 , H04L12/413
CPC分类号： H04B7/15528 , H04L27/2602
摘要： A relay apparatus, terminal apparatus and relay method for relaying signals with a reduced scale of the apparatus, without temporally switching between transmission and reception and with reduced waste of time when relay is performed at the same frequency on a radio communication network on which bidirectional communication is performed. A radio reception section 202 outputs information signals to a switch 208, outputs relay control signals to a demodulation section 204 after subjecting predetermined radio reception processing. The demodulation section 204 demodulates a relay control signal. A relay control signal processing section 206 decides the possibility of relay of information signals and inquires, when the relay is possible, whether the terminal apparatus on the receiving side can receive this information signal or not. Furthermore, the relay control signal processing section 206 connects a switch 208 during the stored relay time. The switch 208 is connected only the information signals to be relayed are received under the control of a relay control section 2063.
摘要翻译： 一种中继装置，终端装置和中继方法，用于在设备的规模缩小的情况下中继信号，而不需要在发送和接收之间进行时间上的切换，并且在双向通信的无线电通信网络上以相同频率执行中继时减少了时间浪费 被执行。 无线接收部202将信息信号输出到开关208，在经过预定的无线接收处理之后，向解调部204输出中继控制信号。 解调部204解调继电器控制信号。 继电器控制信号处理部分206确定信息信号的中继的可能性，并且当继电器可能时，询问接收侧的终端装置是否可以接收该信息信号。 此外，继电器控制信号处理部206在存储的继电器时间期间连接开关208。 在继电器控制部分2063的控制下，开关208只连接待接收的信息信号。
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公开(公告)号：US07254598B2
公开(公告)日：2007-08-07
申请号：US10475090
申请日：2003-03-14
申请人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto
发明人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto
IPC分类号： G06F17/10
CPC分类号： H03H17/0657 , H03H17/0223 , H03H17/0229 , H03H17/06 , H03H17/0621 , H03H2218/085
摘要： An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.
摘要翻译： A / D转换部分对符号率M倍的模拟信号进行过采样，以将模拟信号转换为数字信号。 FIR滤波部分具有两个具有多个延迟元件的延迟元件序列。 两个延迟元件序列具有不同的延迟方向，即正向和反向。 可以切换延迟方向，并且根据具有这种延迟元件序列的有限脉冲响应列，进行卷积计算。 相位确定部确定在判定部中作出判定所使用的相位。 决定部分使用在相位确定部分中确定的相位来对滤波信号做出决定以产生位数据。 因此，实现了数字信号接收装置，其在不增加过采样数量的情况下确定高精度的相位，并且在具有减小的电路规模的情况下执行快速计算。
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公开(公告)号：US20050058104A1
公开(公告)日：2005-03-17
申请号：US10942122
申请日：2004-09-16
IPC分类号： H04L5/14 , H04B1/707 , H04B7/015 , H04B7/15 , H04B7/155 , H04B7/26 , H04J11/00 , H04J13/00 , H04L27/26 , H04W16/26 , H04W84/18 , H04B7/216
CPC分类号： H04B7/15528 , H04L27/2602
摘要： A relay apparatus, terminal apparatus and relay method for relaying signals with a reduced scale of the apparatus, without temporally switching between transmission and reception and with reduced waste of time when relay is performed at the same frequency on a radio communication network on which bidirectional communication is performed. A radio reception section 202 outputs information signals to a switch 208, outputs relay control signals to a demodulation section 204 after subjecting predetermined radio reception processing. The demodulation section 204 demodulates a relay control signal. A relay control signal processing section 206 decides the possibility of relay of information signals and inquires, when the relay is possible, whether the terminal apparatus on the receiving side can receive this information signal or not. Furthermore, the relay control signal processing section 206 connects a switch 208 during the stored relay time. The switch 208 is connected only the information signals to be relayed are received under the control of a relay control section 2063.
摘要翻译： 一种中继装置，终端装置和中继方法，用于在设备的规模缩小的情况下中继信号，而不需要在发送和接收之间进行时间上的切换，并且在双向通信的无线电通信网络上以相同频率执行中继时减少了时间浪费 被执行。 无线接收部202将信息信号输出到开关208，在经过预定的无线接收处理之后，向解调部204输出中继控制信号。 解调部204解调继电器控制信号。 继电器控制信号处理部分206确定信息信号的中继的可能性，并且当继电器可能时，询问接收侧的终端装置是否可以接收该信息信号。 此外，继电器控制信号处理部206在存储的继电器时间期间连接开关208。 在继电器控制部分2063的控制下，开关208只连接待接收的信息信号。
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公开(公告)号：US06593805B2
公开(公告)日：2003-07-15
申请号：US09852240
申请日：2001-05-09
申请人： Yoshinori Kunieda , Kazuo Tomita , Hidekuni Yomo
发明人： Yoshinori Kunieda , Kazuo Tomita , Hidekuni Yomo
IPC分类号： H03D300
CPC分类号： H04L7/0029
摘要： A demodulation apparatus of the present invention comprises: an A/D converter for sampling and quantizing a baseband signal; a transversal filter having time-shifted tap coefficients; a decision unit for decoding the signal which has undergone the transversal filter; and a decision point estimation unit for instructing the transversal filter to select the tap coefficient to be selected based on information from the decision unit. Thus, the demodulation apparatus can operate at the same frequency as a sampling frequency of the A/D converter and can perform decision with accuracy equivalent to an arbitrary oversampling number.
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公开(公告)号：US20100091910A1
公开(公告)日：2010-04-15
申请号：US12527654
申请日：2008-02-20
IPC分类号： H04L27/06
CPC分类号： H03M13/27 , H04J11/003 , H04L1/005 , H04L1/0071 , H04L27/2626 , H04L27/2647
摘要： Provided is a reception device which can reduce a parallel interference canceller processing delay. The reception device (200) includes: a plurality of reception antennas (210A, 210B); an address generation unit (2332) which converts the write-in or read-out order of channel estimation values according to a predetermined rearrangement rule; a channel estimation storage unit (2334) which writes in channel estimation values in the converted order; an address generation unit (2338) which converts the data sequence write-in or read-out order according to the rearrangement rule; a signal storage unit (2340) which writes in or reads out data sequences in the converted order; a replica generation unit (2336) which generates a replica signal by re-modulating the data sequence according to the channel estimation value; a cancel unit (2342) which successively extracts a channel estimation value and a data sequence and generates a stream signal in which the data sequence interference signal is cancelled, by using the channel estimation value, the data sequence, and the replica signal; and an error correction decoding unit (2350) which corrects and decodes an error according to the stream signal.
摘要翻译： 提供一种可以减少并行干扰消除器处理延迟的接收装置。 接收装置（200）包括：多个接收天线（210A，210B）; 地址生成单元，根据预定的重排规则转换信道估计值的写入或读出顺序; 以转换顺序写入信道估计值的信道估计存储单元（2334） 根据重排规则转换数据序列写入或读出顺序的地址生成单元（2338）; 信号存储单元（2340），其以转换的顺序写入或读出数据序列; 复制生成单元，其通过根据所述信道估计值重新调制所述数据序列来生成复制信号; 取消单元（2342），其通过使用信道估计值，数据序列和复制信号，连续地提取信道估计值和数据序列，并生成数据序列干扰信号被消除的流信号; 以及根据流信号校正和解码错误的纠错解码单元（2350）。
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公开(公告)号：US07406140B2
公开(公告)日：2008-07-29
申请号：US10526476
申请日：2003-10-06
CPC分类号： H04B7/15585 , H04B3/23 , H04H20/06 , H04H20/67 , H04L5/0048 , H04L25/0204 , H04L25/0232
摘要： A loop interference canceller that carries out an adaptive operation of responding to time variations of the phase or level of loop interference wave or key station wave at high speed and with high accuracy and reduces the size of an apparatus. The loop interference canceller of the present invention limits the number of data pieces of the transmission path characteristic estimation section, realizes expansion to the entire band not through interpolation but through 0 insertion in a frequency domain and windowing after time domain transformation to reduce the number of data pieces processed and speed up the adaptive operation of the loop interference canceller, and can thereby realize high trackability for time variations of the phase and level of loop interference wave or key station wave, increase the accuracy of processing inside, perform high accuracy cancellation operation, reduce the circuit scale and achieve an advantageous effect of realizing miniaturization of the apparatus.
摘要翻译： 一种环路干扰消除器，其执行响应于高速和高精度的环路干扰波或关键站波的相位或电平的时间变化的自适应操作并且减小设备的尺寸。 本发明的环路干扰消除器限制了传输路径特性估计部分的数据段的数量，不是通过插值实现整个频带的扩展，而是通过频域中的0插入和时域变换后的窗口化来减少 处理数据片并加快环路干扰消除器的自适应操作，从而实现对环路干扰波或关键站波的相位和电平的时间变化的高跟踪性，提高内部处理的精度，执行高精度的取消操作 ，减小电路规模，实现设备小型化的有利效果。
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公开(公告)号：US08265206B2
公开(公告)日：2012-09-11
申请号：US12667579
申请日：2008-07-03
IPC分类号： H04L27/08
CPC分类号： H04L1/0048 , H04L1/0025 , H04L1/005 , H04L1/06 , H04L25/0204 , H04L25/0224 , H04L25/03006 , H04L25/03171
摘要： A radio receiver which performs iterative decoding of a received signal is provided. The radio receiver comprises: a receiving unit receiving a signal on a symbol-by-symbol basis; a demodulation unit (303) demodulating the received signal; a last symbol timing generation unit (308) generating a last symbol timing signal on the basis of the signal demodulated by the demodulation unit (303); a modulation unit (304) modulating the signal demodulated by the demodulation unit (303); and a cancellation unit (306) cancelling an interference component of the received signal using a replica signal generated on the basis of the signal modulated by the modulation unit (304). The modulation unit (304) controls the timing of rearrangement of a data sequence on the basis of the timing of the last symbol. Thus, a radio receiver in which the receiving processing time is reduced can be provided.
摘要翻译： 提供对接收信号执行迭代解码的无线电接收机。 无线电接收机包括：接收单元，以符号为单位接收信号; 解调单元（303），对接收到的信号进行解调; 最后符号定时生成单元，基于由解调单元解调的信号生成最后的符号定时信号; 调制单元（304），调制由解调单元（303）解调的信号; 以及消除单元（306），使用基于由调制单元（304）调制的信号生成的复制信号来消除接收信号的干扰分量。 调制单元（304）基于最后一个符号的定时来控制数据序列的重排的定时。 因此，可以提供其中接收处理时间减少的无线电接收机。
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公开(公告)号：US08233571B2
公开(公告)日：2012-07-31
申请号：US12527654
申请日：2008-02-20
IPC分类号： H03D1/00
CPC分类号： H03M13/27 , H04J11/003 , H04L1/005 , H04L1/0071 , H04L27/2626 , H04L27/2647
摘要： A reception device includes reception antennas and an address generation unit that converts a write-in or read-out order of channel estimation values according to a rearrangement rule. A storage unit writes in or reads out channel estimation values in the converted order, and an address generation unit converts a data sequence write-in or read-out order according to the rearrangement rule. A signal storage unit writes in or reads out data sequences in the converted order, and a replica generation unit generates a replica signal by re-modulating the data sequence according to the channel estimation value. A cancel unit successively generates a stream signal in which a data sequence interference signal is cancelled, by using the channel estimation value, the data sequence, and the replica signal.
摘要翻译： 接收装置包括接收天线和地址生成单元，其根据重排规则转换信道估计值的写入或读出次序。 存储单元以转换的顺序写入或读出信道估计值，地址生成单元根据重排规则转换数据序列写入或读出顺序。 信号存储单元以转换的顺序写入或读出数据序列，并且副本生成单元通过根据信道估计值重新调制数据序列来生成复制信号。 取消单元通过使用信道估计值，数据序列和复制信号，依次生成数据序列干扰信号被消除的流信号。
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公开(公告)号：US20050191961A1
公开(公告)日：2005-09-01
申请号：US10526476
申请日：2003-10-06
IPC分类号： H03H17/04 , H04B3/23 , H04B7/015 , H04B7/155 , H04H20/00 , H04H20/06 , H04H20/67 , H04J11/00 , H04B7/14
CPC分类号： H04B7/15585 , H04B3/23 , H04H20/06 , H04H20/67 , H04L5/0048 , H04L25/0204 , H04L25/0232
摘要： A loop interference canceller that carries out an adaptive operation of responding to time variations of the phase or level of loop interference wave or key station wave at high speed and with high accuracy and reduces the size of an apparatus. The loop interference canceller of the present invention limits the number of data pieces of the transmission path characteristic estimation section, realizes expansion to the entire band not through interpolation but through 0 insertion in a frequency domain and windowing after time domain transformation to reduce the number of data pieces processed and speed up the adaptive operation of the loop interference canceller, and can thereby realize high trackability for time variations of the phase and level of loop interference wave or key station wave, increase the accuracy of processing inside, perform high accuracy cancellation operation, reduce the circuit scale and achieve an advantageous effect of realizing miniaturization of the apparatus.
摘要翻译： 一种环路干扰消除器，其执行响应于高速和高精度的环路干扰波或关键站波的相位或电平的时间变化的自适应操作并且减小设备的尺寸。 本发明的环路干扰消除器限制了传输路径特性估计部分的数据段的数量，不是通过插值实现整个频带的扩展，而是通过频域中的0插入和时域变换后的窗口化来减少 处理数据片并加快环路干扰消除器的自适应操作，从而实现对环路干扰波或关键站波的相位和电平的时间变化的高跟踪性，提高内部处理的精度，执行高精度的取消操作 ，减小电路规模，实现设备小型化的有利效果。
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