公开(公告)号：US08222109B2

公开(公告)日：2012-07-17

申请号：US12760152

申请日：2010-04-14

申请人： Hideo Yamamoto ,  Kei Takehara

发明人： Hideo Yamamoto ,  Kei Takehara

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734

摘要： A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.

摘要翻译： 根据本发明的制造半导体器件的方法包括通过在形成在衬底上的外延层中进一步蚀刻第一沟槽来形成第一沟槽和第二沟槽，延伸第二沟槽的宽度，通过第二沟槽的宽度形成氧化膜 氧化延伸的第二沟槽，并且填充第一沟槽中的电极材料和包括其中形成的氧化膜的第二沟槽。 根据本发明的制造半导体器件的方法能够制造提高漏极和源极之间的耐受电压并降低导通电阻的半导体器件。

公开(公告)号：US08609493B2

公开(公告)日：2013-12-17

申请号：US13527179

申请日：2012-06-19

申请人： Hideo Yamamoto ,  Kei Takehara

发明人： Hideo Yamamoto ,  Kei Takehara

IPC分类号： H01L21/00

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734

摘要： A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.

摘要翻译： 根据本发明的制造半导体器件的方法包括通过在形成在衬底上的外延层中进一步蚀刻第一沟槽来形成第一沟槽和第二沟槽，延伸第二沟槽的宽度，通过第二沟槽的宽度形成氧化膜 氧化延伸的第二沟槽，并且填充第一沟槽中的电极材料和包括其中形成的氧化膜的第二沟槽。 根据本发明的制造半导体器件的方法能够制造提高漏极和源极之间的耐受电压并降低导通电阻的半导体器件。

公开(公告)号：US20120282745A1

公开(公告)日：2012-11-08

申请号：US13527179

申请日：2012-06-19

申请人： Hideo Yamamoto ,  Kei Takehara

发明人： Hideo Yamamoto ,  Kei Takehara

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734

摘要： A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.

摘要翻译： 根据本发明的制造半导体器件的方法包括通过在形成在衬底上的外延层中进一步蚀刻第一沟槽来形成第一沟槽和第二沟槽，延伸第二沟槽的宽度，通过第二沟槽的宽度形成氧化膜 氧化延伸的第二沟槽，并且填充第一沟槽中的电极材料和包括其中形成的氧化膜的第二沟槽。 根据本发明的制造半导体器件的方法能够制造提高漏极和源极之间的耐受电压并降低导通电阻的半导体器件。

公开(公告)号：US20120043603A1

公开(公告)日：2012-02-23

申请号：US13317697

申请日：2011-10-26

申请人： Kei Takehara

发明人： Kei Takehara

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.

摘要翻译： 半导体器件包括第一导电型半导体层，形成在第一导电型半导体层的上部中的第二导电类型的基极区域，第一至第三沟槽穿透基极区域并达到 第一导电型半导体层，第一至第三沟槽彼此连接，埋置在第一至第三沟槽中的源极互连层，源极互连层包括突出部分，埋置在第一沟槽中的栅电极和 第三沟槽，并且形成在源极互连层上，与源极互连层的突出部分接触的源极金属和与第三沟槽中的栅电极接触的栅极金属。 源极金属与第二沟槽的突出部之间的接触面形成为高于第三沟槽处的栅极金属与栅电极之间的接触面。

公开(公告)号：US08071445B2

公开(公告)日：2011-12-06

申请号：US12662485

申请日：2010-04-20

申请人： Kei Takehara

发明人： Kei Takehara

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8236

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source interconnect layer is connected to a source electrode formed in the transistor region immediately above the trench. A gate extending region is provided outside the source extending region, and the gate electrode and a gate interconnect layer are connected. The gate electrode is formed by performing etchback without forming a resist pattern, after a polysilicon film is formed. Here, the polysilicon film remains like a side-wall on the sidewall of the portion of the source interconnect layer protruding from the upper end of the trench.

摘要翻译： 在晶体管区域中，源极互连层和栅电极被埋在沟槽中。 源极延伸区域邻近晶体管区域或晶体管区域设置，源极互连层设计成从沟槽的上端突出。 该源极互连层连接到形成在沟槽正上方的晶体管区域中的源电极。 栅极延伸区域设置在源极延伸区域的外部，并且栅极电极和栅极互连层被连接。 在形成多晶硅膜之后，通过进行回蚀而形成栅电极而不形成抗蚀剂图案。 这里，多晶硅膜保持像源极互连层的从沟槽的上端突出的部分的侧壁上的侧壁。

公开(公告)号：US07863679B2

公开(公告)日：2011-01-04

申请号：US11976161

申请日：2007-10-22

申请人： Kei Takehara

发明人： Kei Takehara

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66734

摘要： A vertical power MOSFET includes a semiconductor substrate including a trench, a gate electrode layer having a prescribed impurity concentration and being formed inside the trench, and a cap insulating layer having a lower impurity concentration than the impurity concentration of the gate electrode layer and covering the gate electrode layer to provide insulation.

摘要翻译： 垂直功率MOSFET包括：半导体衬底，包括沟槽，具有规定的杂质浓度的栅极电极层，并形成在沟槽内;以及帽绝缘层，其杂质浓度低于栅极电极层的杂质浓度，并覆盖 栅电极层提供绝缘。

公开(公告)号：US08748261B2

公开(公告)日：2014-06-10

申请号：US13317697

申请日：2011-10-26

申请人： Kei Takehara

发明人： Kei Takehara

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/311

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.

摘要翻译： 半导体器件包括第一导电型半导体层，形成在第一导电型半导体层的上部中的第二导电类型的基极区域，第一至第三沟槽穿透基极区域并达到 第一导电型半导体层，第一至第三沟槽彼此连接，埋置在第一至第三沟槽中的源极互连层，源极互连层包括突出部分，埋置在第一沟槽中的栅电极和 第三沟槽，并且形成在源极互连层上，与源极互连层的突出部分接触的源极金属和与第三沟槽中的栅电极接触的栅极金属。 源极金属与第二沟槽的突出部之间的接触面形成为高于第三沟槽处的栅极金属与栅电极之间的接触面。

公开(公告)号：US20100270613A1

公开(公告)日：2010-10-28

申请号：US12662485

申请日：2010-04-20

申请人： Kei Takehara

发明人： Kei Takehara

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source interconnect layer is connected to a source electrode formed in the transistor region immediately above the trench. A gate extending region is provided outside the source extending region, and the gate electrode and a gate interconnect layer are connected. The gate electrode is formed by performing etchback without forming a resist pattern, after a polysilicon film is formed. Here, the polysilicon film remains like a side-wall on the sidewall of the portion of the source interconnect layer protruding from the upper end of the trench.

摘要翻译： 在晶体管区域中，源极互连层和栅电极被埋在沟槽中。 源极延伸区域邻近晶体管区域或晶体管区域设置，源极互连层设计成从沟槽的上端突出。 该源极互连层连接到形成在沟槽正上方的晶体管区域中的源电极。 栅极延伸区域设置在源极延伸区域的外部，并且栅极电极和栅极互连层被连接。 在形成多晶硅膜之后，通过进行回蚀而形成栅电极而不形成抗蚀剂图案。 这里，多晶硅膜保持像源极互连层的从沟槽的上端突出的部分的侧壁上的侧壁。

公开(公告)号：US20080093665A1

公开(公告)日：2008-04-24

申请号：US11976161

申请日：2007-10-22

申请人： Kei Takehara

发明人： Kei Takehara

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66734

摘要： A vertical power MOSFET includes a semiconductor substrate including a trench, a gate electrode layer having a prescribed impurity concentration and being formed inside the trench, and a cap insulating layer having a lower impurity concentration than the impurity concentration of the gate electrode layer and covering the gate electrode layer to provide insulation.

摘要翻译： 垂直功率MOSFET包括：半导体衬底，包括沟槽，具有规定的杂质浓度的栅极电极层，并形成在沟槽内;以及帽绝缘层，其杂质浓度低于栅极电极层的杂质浓度，并覆盖 栅电极层提供绝缘。

公开(公告)号：US5340459A

公开(公告)日：1994-08-23

申请号：US978982

申请日：1992-11-19

申请人： Kei Takehara

发明人： Kei Takehara

IPC分类号： C23C14/34 ,  C23C14/00 ,  C23C14/54 ,  H01L21/203

CPC分类号： H01J37/3244 ,  C23C14/0063

摘要： A reactive sputtering system is provided with a side gas distribution pipe for introducing a reactive gas and argon gas into a reaction chamber and a ring-shaped gas distribution pipe for introducing the argon gas or reactive gas into the reaction chamber independently of the side gas distribution pipe, whereby the concentration of the reactive gas can be controlled with respect to a target in the diameter direction thereof to equalize the reaction between the reactive gas and the target material above the surface of the target and thus to provide an improved uniformity of the quality film.

摘要翻译： 反应性溅射系统设置有用于将反应气体和氩气引入反应室的侧气体分配管和用于将氩气或反应气体独立于侧气体分配引入反应室的环形气体分配管 从而能够相对于目标在其直径方向上控制反应气体的浓度，以使反应气体和目标材料之间的反应在目标物表面之上均匀化，从而提供质量的均匀性 电影。