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公开(公告)号：US07705408B2
公开(公告)日：2010-04-27
申请号：US11191929
申请日：2005-07-29
申请人： Hideo Yamamoto , Kenya Kobayashi
发明人： Hideo Yamamoto , Kenya Kobayashi
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4238 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： A MOSFET has a base layer and a source layer in a cell surrounded by a trench gate formed in a semiconductor substrate. A trench contact is formed through the source layer and the base layer. The gate is polygonal such as square. The trench contact is thin and linear so as to increase embedding characteristics. Further, the trench contact is ring or cross shaped so as to reduce a source length.
摘要翻译： MOSFET在由半导体衬底中形成的沟槽栅围绕的单元中具有基极层和源极层。 通过源极层和基极层形成沟槽接触。 门是多边形，如正方形。 沟槽接触是薄且线性的，以增加嵌入特性。 此外，沟槽接触是环形或十字形的，以便减少源长度。
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公开(公告)号：US20080067625A1
公开(公告)日：2008-03-20
申请号：US11898583
申请日：2007-09-13
申请人： Hideo Yamamoto , Kenya Kobayashi
发明人： Hideo Yamamoto , Kenya Kobayashi
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L27/0629 , H01L29/0696 , H01L29/41741 , H01L29/42376 , H01L29/4238 , H01L29/7808 , H01L29/7813
摘要： An improved semiconductor device having a gate electrode buried in a trench that a short circuit is hardly generated between a gate electrode and a source electrode at a termination of the gate electrode. A trench is formed in a semiconductor substrate. A gate electrode and a buried insulating film are buried in the trench. A source electrode is provided above the gate electrode via the buried insulating film. At the termination of the gate electrode, an interlayer insulating film is provided between the buried insulating film and the source electrode in such a way that the interlayer insulating film strides over the termination of the trench. Both of the buried insulating film and the interlayer insulating film function as an insulating film and prevent a short circuit at the termination of the gate electrode.
摘要翻译： 一种改进的半导体器件，其具有掩埋在沟槽中的栅电极，在栅电极的端接处在栅电极和源电极之间几乎不产生短路。 在半导体衬底中形成沟槽。 栅电极和掩埋绝缘膜埋在沟槽中。 源电极经由掩埋绝缘膜设置在栅电极上方。 在栅电极的终止处，在掩埋绝缘膜和源电极之间设置层间绝缘膜，使得层间绝缘膜跨越沟槽的终端。 埋入绝缘膜和层间绝缘膜两者都用作绝缘膜，并且防止在栅电极终止时的短路。
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公开(公告)号：US20090072300A1
公开(公告)日：2009-03-19
申请号：US12232074
申请日：2008-09-10
申请人： Hideo Yamamoto , Kenya Kobayashi , Atsushi Kaneko
发明人： Hideo Yamamoto , Kenya Kobayashi , Atsushi Kaneko
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L27/0727 , H01L29/0696 , H01L29/1095 , H01L29/7808
摘要： The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFET 100 comprises a plurality of gate trenches 7 which is arranged in stripes, an array which is sandwiched with the plurality of gate trenches 7 and includes N+ source regions 4N+ and P+ base contact regions 5P+, and a diode region (anode region 6P+) which is formed so as to contact with two gate trenches 7. The N+ source regions 4N+ and the base contact regions 5P+ are alternately arranged along a longitudinal direction of the gate trench 7. Size of the diode region (anode region 6P+) corresponds to at least one of the N+ source regions 4N+ and two of the P+ base contact regions 5P+.
摘要翻译： 本发明提供了一种具有条纹沟槽栅极结构的垂直MOSFET，其可以在不增加Ron的情况下确保雪崩电阻。 垂直MOSFET100包括多个栅极沟槽7，栅极沟槽7被布置成阵列，该阵列夹在多个栅极沟槽7之间并包括N +源极区域4N +和P +基极接触区域5P +，二极管区域（阳极区域6P + ）形成为与两个栅极沟槽7接触.N +源极区域4N +和基极接触区域5P +沿着栅极沟槽7的纵向方向交替排列。二极管区域（阳极区域6P +）的尺寸对应于 N +源极区域4N +和P +基极接触区域5P + +中的至少一个。
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公开(公告)号：US08072026B2
公开(公告)日：2011-12-06
申请号：US12659454
申请日：2010-03-09
IPC分类号： H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L29/00
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.
摘要翻译： 一种半导体器件，包括第二导电类型的半导体层，形成在半导体层中的第一导电类型的第一扩散区域，选择性地形成在第一扩散区域中的第二导电类型的第二扩散区域，形成在 半导体层，形成在具有绝缘体的沟槽中的多晶硅，形成在多晶硅上的第一氧化物膜，使得第一氧化物膜被埋在沟槽中，形成在第一氧化物膜上的第二氧化物膜，使得第二氧化物 膜被埋在沟槽中，以及形成在第二氧化物膜上的可流动的绝缘膜，使得可流动的绝缘膜被埋在沟槽中。
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公开(公告)号：US07947556B2
公开(公告)日：2011-05-24
申请号：US12801806
申请日：2010-06-25
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译： 一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜 沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。 该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。
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公开(公告)号：US07776693B2
公开(公告)日：2010-08-17
申请号：US11905078
申请日：2007-09-27
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译： 一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜 沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。 该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。
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公开(公告)号：US07704827B2
公开(公告)日：2010-04-27
申请号：US11984043
申请日：2007-11-13
IPC分类号： H01L21/8242
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n− epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.
摘要翻译： 通过外延生长在n +半导体衬底上形成外延层。 栅极沟槽形成在栅极沟槽的表面，使得栅极沟槽的底部到达外延层的中间。 栅极绝缘体形成在栅极沟槽的内壁上，并且栅极沟槽中形成多晶硅，栅极绝缘体插入其间。 在多晶硅和n外延层的表面上形成HTO膜。 此时，通过HTO膜对外延层进行离子种植。 因此，形成p扩散基极层，n +扩散源极层，n +扩散源极层。 在HTO膜上形成CVD氧化膜。 在具有流动性的BPSG沉积在CVD氧化物膜上之后，通过900-1100摄氏度的热处理将BPSG膜平坦化。
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公开(公告)号：US20080081422A1
公开(公告)日：2008-04-03
申请号：US11905078
申请日：2007-09-27
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译： 一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜 沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。 该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。
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公开(公告)号：US20060226475A1
公开(公告)日：2006-10-12
申请号：US11191929
申请日：2005-07-29
申请人： Hideo Yamamoto , Kenya Kobayashi
发明人： Hideo Yamamoto , Kenya Kobayashi
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4238 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： A MOSFET has a base layer and a source layer in a cell surrounded by a trench gate formed in a semiconductor substrate. A trench contact is formed through the source layer and the base layer. The gate is polygonal such as square. The trench contact is thin and linear so as to increase embedding characteristics. Further, the trench contact is ring or cross shaped so as to reduce a source length.
摘要翻译： MOSFET在由半导体衬底中形成的沟槽栅包围的单元中具有基极层和源极层。 通过源极层和基极层形成沟槽接触。 门是多边形，如正方形。 沟槽接触是薄且线性的，以增加嵌入特性。 此外，沟槽接触是环形或十字形的，以便减少源长度。
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公开(公告)号：US20100267211A1
公开(公告)日：2010-10-21
申请号：US12801806
申请日：2010-06-25
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
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