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公开(公告)号：US20070138571A1
公开(公告)日：2007-06-21
申请号：US11544653
申请日：2006-10-10
申请人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
发明人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L21/823456 , H01L21/823412 , H01L21/823462 , H01L27/10894
摘要： A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
摘要翻译： 在用于形成第一MIS晶体管的阈值控制层的相同条件下形成第二MIS晶体管的阈值控制层。 在与形成第三晶体管的LDD区域相同的条件下形成第二MIS晶体管的LLD区域。
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公开(公告)号：US07932153B2
公开(公告)日：2011-04-26
申请号：US12605875
申请日：2009-10-26
申请人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
发明人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
IPC分类号： H01L21/8236
CPC分类号： H01L21/823456 , H01L21/823412 , H01L21/823462 , H01L27/10894
摘要： A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
摘要翻译： 在用于形成第一MIS晶体管的阈值控制层的相同条件下形成第二MIS晶体管的阈值控制层。 在与形成第三晶体管的LDD区域相同的条件下形成第二MIS晶体管的LLD区域。
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公开(公告)号：US07763922B2
公开(公告)日：2010-07-27
申请号：US11152109
申请日：2005-06-15
IPC分类号： H01L31/062
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10888 , H01L28/91
摘要： A capacitor of a semiconductor memory of the present invention includes: a lower electrode which covers the surface of a storage node hole from the bottom to at least one of the sidewalls up to a level lower than the top surface of a second interlayer insulating film; a capacitive insulating film which covers the lower electrode; and an upper electrode which covers the capacitive insulating film.
摘要翻译： 本发明的半导体存储器的电容器包括：下电极，其从底部到至少一个侧壁覆盖存储节点孔的表面直到比第二层间绝缘膜的顶表面低的水平; 覆盖下电极的电容绝缘膜; 以及覆盖电容绝缘膜的上电极。
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公开(公告)号：US07622777B2
公开(公告)日：2009-11-24
申请号：US11544653
申请日：2006-10-10
申请人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
发明人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
IPC分类号： H01L27/088
CPC分类号： H01L21/823456 , H01L21/823412 , H01L21/823462 , H01L27/10894
摘要： A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
摘要翻译： 在用于形成第一MIS晶体管的阈值控制层的相同条件下形成第二MIS晶体管的阈值控制层。 在与形成第三晶体管的LDD区域相同的条件下形成第二MIS晶体管的LLD区域。
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公开(公告)号：US20060076600A1
公开(公告)日：2006-04-13
申请号：US11188866
申请日：2005-07-26
IPC分类号： H01L29/94
CPC分类号： H01L21/02186 , H01L21/02271 , H01L21/31122 , H01L21/318 , H01L21/32135 , H01L27/10811 , H01L27/10888 , H01L27/10894 , H01L28/60
摘要： In a method for fabricating a semiconductor device according to the present invention, a groove is formed in a second interlayer insulating film, and then a storage electrode is formed which covers bottom and side surfaces of the groove. A capacitor insulating film is formed on the storage electrode, and a CVD method at a low temperature of 400° C. or lower and annealing with ammonia are repeated to form a TiOxNy film on the capacitor insulating film. A TiN film is formed on the TiOxNy film, and the TiN film is etched using the TiOxNy film as a stopper. The exposed TiOxNy film is then removed to form a plate electrode made of the TiOxNy film and the TiN film.
摘要翻译： 在根据本发明的半导体器件的制造方法中，在第二层间绝缘膜中形成凹槽，然后形成覆盖凹槽的底部和侧表面的存储电极。 在存储电极上形成电容器绝缘膜，并且在400℃或更低的低温和用氨退火的CVD方法被重复以形成TiO 2 x N y / SUB>电容器绝缘膜上。 在TiO 2膜层上形成TiN膜，并使用TiO 2 X N y膜蚀刻TiN膜， / SUB膜作为塞子。 然后除去暴露的TiO 2，N 2 O 3膜，以形成由TiO 2，N 2 O 3， 薄膜和TiN薄膜。
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公开(公告)号：US07795662B2
公开(公告)日：2010-09-14
申请号：US11822921
申请日：2007-07-11
申请人： Hideyuki Arai , Takashi Nakabayashi
发明人： Hideyuki Arai , Takashi Nakabayashi
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852 , H01L27/10888
摘要： A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and the upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.
摘要翻译： 半导体存储器件具有形成在半导体衬底上并具有设置在膜中的电容器开口部分的第一层间绝缘膜，以及形成在电容器开口部分的底部和侧面上并由下部电极构成的电容元件， 绝缘膜和上电极。 通过第一层间绝缘膜形成位线接触插头。 下电极，电容绝缘膜和位于位线接触插塞的一侧的上电极的至少一部分位于第一层间绝缘膜的表面下方，下电极，电容绝缘层 膜，并且上电极位于电容器开口部分的侧面上。 上电极仅形成在电容器开口部的底部和侧面上。
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公开(公告)号：US07737480B2
公开(公告)日：2010-06-15
申请号：US11826089
申请日：2007-07-12
申请人： Ryo Nakagawa , Takashi Nakabayashi , Hideyuki Arai
发明人： Ryo Nakagawa , Takashi Nakabayashi , Hideyuki Arai
IPC分类号： H01L31/062
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10811
摘要： A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.
摘要翻译： 半导体存储器件包括：形成在衬底中的晶体管; 形成在所述晶体管的源/漏区之一上的电容器; 形成在衬底上并沿晶体管的栅极长度方向延伸的位线; 连接源极/漏极区域和电容器之一的第一导电插头; 连接到未连接到第一导电插头的另一个源极/漏极区域的第二导电插头; 以及形成在所述第二导电插头上并连接到所述位线的第三导电插塞。 第三导电插塞的中心轴线在晶体管的栅极宽度方向上从第二导电插头的中心轴线移位。
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公开(公告)号：US20080035975A1
公开(公告)日：2008-02-14
申请号：US11826089
申请日：2007-07-12
申请人： Ryo Nakagawa , Takashi Nakabayashi , Hideyuki Arai
发明人： Ryo Nakagawa , Takashi Nakabayashi , Hideyuki Arai
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10811
摘要： A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.
摘要翻译： 半导体存储器件包括：形成在衬底中的晶体管; 形成在所述晶体管的源/漏区之一上的电容器; 形成在衬底上并沿晶体管的栅极长度方向延伸的位线; 连接源极/漏极区域和电容器之一的第一导电插头; 连接到未连接到第一导电插头的另一个源极/漏极区域的第二导电插头; 以及形成在所述第二导电插头上并连接到所述位线的第三导电插塞。 第三导电插塞的中心轴线在晶体管的栅极宽度方向上从第二导电插头的中心轴线移位。
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公开(公告)号：US20070275529A1
公开(公告)日：2007-11-29
申请号：US11702593
申请日：2007-02-06
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823412 , H01L29/7833
摘要： After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then, the protective insulating film formed on the second active region is removed. Next, an insulating film to be a second gate insulating film is formed on the second active region, and then, the insulating film to be the first gate insulating film formed on the third active region is removed. Finally, an insulating film to be a third gate insulating film is formed on the third active region.
摘要翻译： 在第一至第三有源区上形成保护绝缘膜之后，去除形成在第一和第三有源区上的保护绝缘膜。 随后，在第一和第三有源区域中的每一个上形成作为第一栅极绝缘膜的绝缘膜，然后去除形成在第二有源区上的保护绝缘膜。 接下来，在第二有源区上形成作为第二栅极绝缘膜的绝缘膜，然后除去形成在第三有源区上的作为第一栅极绝缘膜的绝缘膜。 最后，在第三有源区上形成作为第三栅极绝缘膜的绝缘膜。
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公开(公告)号：US20060086960A1
公开(公告)日：2006-04-27
申请号：US11152109
申请日：2005-06-15
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10888 , H01L28/91
摘要： A capacitor of a semiconductor memory of the present invention includes: a lower electrode which covers the surface of a storage node hole from the bottom to at least one of the sidewalls up to a level lower than the top surface of a second interlayer insulating film; a capacitive insulating film which covers the lower electrode; and an upper electrode which covers the capacitive insulating film.
摘要翻译： 本发明的半导体存储器的电容器包括：下电极，其从底部到至少一个侧壁覆盖存储节点孔的表面直到比第二层间绝缘膜的顶表面低的水平; 覆盖下电极的电容绝缘膜; 以及覆盖电容绝缘膜的上电极。
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