公开(公告)号：US07843013B2

公开(公告)日：2010-11-30

申请号：US12141530

申请日：2008-06-18

申请人： Ryo Nakagawa ,  Takayuki Yamada

发明人： Ryo Nakagawa ,  Takayuki Yamada

IPC分类号： H01L29/76 ,  H01L29/00

CPC分类号： H01L21/823807 ,  H01L27/0629 ,  H01L29/7843

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 由隔离区包围的有源区，分别包括p型和n型区; 形成在包括p型区域并包括n型栅电极的有源区中的NMOS晶体管; 形成在包括n型区域并包括p型栅电极的有源区中的PMOS晶体管; 以及形成在隔离区上的p型电阻器。 p型电阻器的内应力大于p型栅电极的内应力。

公开(公告)号：US07737480B2

公开(公告)日：2010-06-15

申请号：US11826089

申请日：2007-07-12

申请人： Ryo Nakagawa ,  Takashi Nakabayashi ,  Hideyuki Arai

发明人： Ryo Nakagawa ,  Takashi Nakabayashi ,  Hideyuki Arai

IPC分类号： H01L31/062

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10811

摘要： A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.

摘要翻译： 半导体存储器件包括：形成在衬底中的晶体管; 形成在所述晶体管的源/漏区之一上的电容器; 形成在衬底上并沿晶体管的栅极长度方向延伸的位线; 连接源极/漏极区域和电容器之一的第一导电插头; 连接到未连接到第一导电插头的另一个源极/漏极区域的第二导电插头; 以及形成在所述第二导电插头上并连接到所述位线的第三导电插塞。 第三导电插塞的中心轴线在晶体管的栅极宽度方向上从第二导电插头的中心轴线移位。

公开(公告)号：US20080035975A1

公开(公告)日：2008-02-14

申请号：US11826089

申请日：2007-07-12

申请人： Ryo Nakagawa ,  Takashi Nakabayashi ,  Hideyuki Arai

发明人： Ryo Nakagawa ,  Takashi Nakabayashi ,  Hideyuki Arai

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10811

摘要： A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.

摘要翻译： 半导体存储器件包括：形成在衬底中的晶体管; 形成在所述晶体管的源/漏区之一上的电容器; 形成在衬底上并沿晶体管的栅极长度方向延伸的位线; 连接源极/漏极区域和电容器之一的第一导电插头; 连接到未连接到第一导电插头的另一个源极/漏极区域的第二导电插头; 以及形成在所述第二导电插头上并连接到所述位线的第三导电插塞。 第三导电插塞的中心轴线在晶体管的栅极宽度方向上从第二导电插头的中心轴线移位。

公开(公告)号：US07982372B2

公开(公告)日：2011-07-19

申请号：US12326353

申请日：2008-12-02

申请人： Akio Machida ,  Ryo Nakagawa ,  Yasuhide Matsuo

发明人： Akio Machida ,  Ryo Nakagawa ,  Yasuhide Matsuo

IPC分类号： H01L41/04 ,  H01L41/08

CPC分类号： H01L41/107 ,  H01L41/053

摘要： A piezoelectric transformer includes: a piezoelectric transducer on whose outer surface an electrode is formed; a case housing the piezoelectric transducer; a terminal disposed to face the electrode; an elastic member in contact with both the electrode and the terminal in the case and having conductivity to bring the electrode and the terminal into mutual continuity; and a folder formed in the case and fixedly holding the elastic member to press-fit the elastic member between the electrode and the terminal.

摘要翻译： 压电变压器包括：压电换能器，其外表面上形成有电极; 容纳压电换能器的壳体; 设置成面对电极的端子; 在壳体中与电极和端子接触的弹性构件，并且具有使电极和端子相互连续的导电性; 以及形成在壳体中的夹子，并且固定地保持弹性构件以将弹性构件压配合在电极和端子之间。

公开(公告)号：US20110101461A1

公开(公告)日：2011-05-05

申请号：US12915377

申请日：2010-10-29

申请人： Masahiko TAKEUCHI ,  Ryo NAKAGAWA ,  Kazuo NAKAGAWA

发明人： Masahiko TAKEUCHI ,  Ryo NAKAGAWA ,  Kazuo NAKAGAWA

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/11 ,  H01L21/76895 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/1104

摘要： The present invention presupposes a MIPS electrode in which a gate electrode of a MISFET is made up of a stacked film of a metal film and a polysilicon film. Then, by a first characteristic point that a gate contact hole is formed to have an opening diameter larger than a gate length of the gate electrode of the MIPS electrode and a second characteristic point that a concave portion is formed in a side surface of the metal film constituting the gate electrode, the further reduction of the gate resistance (parasitic resistance) and the improvement of the connection reliability between the gate electrode and the gate plug can be achieved.

摘要翻译： 本发明提出了一种MIPS电极，其中MISFET的栅电极由金属膜和多晶硅膜的叠层膜构成。 然后，通过形成栅极接触孔的开口直径大于MIPS电极的栅电极的栅极长度的第一特征点和在金属的侧表面形成凹部的第二特征点 可以实现构成栅电极的膜，栅极电阻（寄生电阻）的进一步降低以及栅电极和栅极插头之间的连接可靠性的提高。

公开(公告)号：US20070103036A1

公开(公告)日：2007-05-10

申请号：US11595499

申请日：2006-11-10

申请人： Ryo Nakagawa ,  Yasuhide Matsuo

发明人： Ryo Nakagawa ,  Yasuhide Matsuo

IPC分类号： H01L41/107

CPC分类号： H01L41/107 ,  H01L41/047

摘要： There is provided with a piezoelectric transformer which does not require a marking operation, is easy to manufacture, and is capable of reducing costs. After the piezoelectric transformer is manufactured, a shape of secondary side electrodes on the outer end is made so that a polarization direction can be recognized at the time of printing the secondary side electrodes without marking by a separate step to recognize the polarity on the primary side.

摘要翻译： 提供了不需要标记操作的压电变压器，易于制造，并且能够降低成本。 在制造压电变压器之后，形成外端上的次级侧电极的形状，使得在打印次级侧电极时可以识别出偏振方向，而无需通过单独的步骤进行标记以识别初级侧的极性 。

公开(公告)号：US20060043888A1

公开(公告)日：2006-03-02

申请号：US11208676

申请日：2005-08-22

申请人： Ryo Nakagawa ,  Shinichiro Morikawa ,  Yuichi Iwase

发明人： Ryo Nakagawa ,  Shinichiro Morikawa ,  Yuichi Iwase

IPC分类号： H05B33/00 ,  H01J1/62

CPC分类号： H01L27/322 ,  H01L51/5246 ,  H01L51/5253 ,  H01L51/5281 ,  H01L2251/558

摘要： A display unit in which viewing angle characteristics such as color shift and luminance unevenness depending on the viewing angle are improved and a manufacturing method thereof are provided. A display unit includes a driving panel having a plurality of light emitting devices arranged in a grid on a device substrate, a sealing panel including a sealing substrate, and a transparent resin layer which is sandwiched between the sealing panel and the driving panel. The transparent resin layer has a thickness L1 satisfying Mathematical formula 1. L 1 ≦ { ( L PITCH -   ⁢ L CF ) +   ⁢ ( L CF -   ⁢ L EL ) /   ⁢ 2 } +   ⁢ HK tan ⁢ { a ⁢   ⁢ sin ( 1 n ) } Mathematical ⁢   ⁢ formula ⁢   ⁢ 1

公开(公告)号：US20210205344A1

公开(公告)日：2021-07-08

申请号：US17056552

申请日：2018-10-03

申请人： Masamitsu MORIWAKI ,  Kentaro KUMOI ,  Ryo NAKAGAWA ,  Miki SAGISAKA ,  Makoto OZEKI

发明人： Masamitsu MORIWAKI ,  Kentaro KUMOI ,  Ryo NAKAGAWA ,  Miki SAGISAKA ,  Makoto OZEKI

IPC分类号： A61K31/7048 ,  A61K47/69 ,  A61K8/60 ,  A61K8/73 ,  A23L29/30 ,  A23L33/105 ,  A23L27/00 ,  A23L5/41 ,  A23L2/60

摘要： A composition containing one or more materials selected from the group consisting of fatty acids, proteins, peptides, amino acids, vitamins, minerals, alcohols, sweeteners, acidulants, antioxidants, thickening stabilizer, and surfactants, and a flavonoid-cyclodextrin inclusion compound, wherein the inclusion compound contains an inclusion compound obtained by treating a flavonoid having a rhamnoside structure with an enzyme having rhamnosidase activity in the presence of a cyclodextrin. According to the present invention, the bitterness and the changes in color tones originated from flavonoids can be inhibited, and foodstuff or the like having an unpleasant taste can be improved, so that the present invention can be suitably utilized in fields such as medicaments, foodstuff, health foods, foods for specified health use, and cosmetics.

公开(公告)号：US07915131B2

公开(公告)日：2011-03-29

申请号：US12914026

申请日：2010-10-28

申请人： Ryo Nakagawa ,  Takayuki Yamada

发明人： Ryo Nakagawa ,  Takayuki Yamada

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/823807 ,  H01L27/0629 ,  H01L29/7843

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 由隔离区包围的有源区，分别包括p型和n型区; 形成在包括p型区域并包括n型栅电极的有源区中的NMOS晶体管; 形成在包括n型区域并包括p型栅电极的有源区中的PMOS晶体管; 以及形成在隔离区上的p型电阻器。 p型电阻器的内应力大于p型栅电极的内应力。

公开(公告)号：US20110039379A1

公开(公告)日：2011-02-17

申请号：US12914026

申请日：2010-10-28

申请人： Ryo NAKAGAWA ,  Takayuki Yamada

发明人： Ryo NAKAGAWA ,  Takayuki Yamada

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L27/0629 ,  H01L29/7843

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 由隔离区包围的有源区，分别包括p型和n型区; 形成在包括p型区域并包括n型栅电极的有源区中的NMOS晶体管; 形成在包括n型区域并包括p型栅电极的有源区中的PMOS晶体管; 以及形成在隔离区上的p型电阻器。 p型电阻器的内应力大于p型栅电极的内应力。