公开(公告)号：US5521536A

公开(公告)日：1996-05-28

申请号：US286270

申请日：1994-08-05

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

IPC分类号： H03K19/0175

CPC分类号： H03K19/017545

摘要： In signal transmission lines among logic circuits employed in a semiconductor integrated circuit device, a voltage driver circuit is provided with such a wiring whose length is short, and the function of the signal receiving circuit is achieved by a logic circuit capable of responding to a voltage appearing at a terminal of the wiring. On the other hand, a source terminal of such a wiring whose length is long and whose resistance is high, is voltage-driven by the voltage driver circuit in response to the output voltage of the logic circuit. A current sense circuit is provided with a terminal of this long length wiring, which senses a current flowing through this long length wiring to be converted into a voltage. Both an output resistance of the voltage driver circuit and an input resistance of the current sense circuit are made lower than a DC resistance of this long length wiring.

摘要翻译： 在半导体集成电路装置中使用的逻辑电路之间的信号传输线中，电压驱动电路具有长度短的布线，信号接收电路的功能由能够对电压进行响应的逻辑电路 出现在接线端子处。 另一方面，长度长且电阻较高的布线的源极端子由电压驱动电路根据逻辑电路的输出电压进行电压驱动。 电流检测电路设置有该长度布线的端子，该端子感测流过该长度布线的电流，以转换成电压。 电压驱动电路的输出电阻和电流检测电路的输入电阻均低于该长度布线的直流电阻。

公开(公告)号：US5403783A

公开(公告)日：1995-04-04

申请号：US168762

申请日：1993-12-16

申请人： Keiichiro Nakanishi ,  Tsuneyo Chiba ,  Hiroyuki Itoh ,  Tatsuya Saitoh ,  Takeshi Kato

发明人： Keiichiro Nakanishi ,  Tsuneyo Chiba ,  Hiroyuki Itoh ,  Tatsuya Saitoh ,  Takeshi Kato

IPC分类号： H01L21/48 ,  H01L23/427 ,  H01L23/433 ,  H01L23/473 ,  H01L21/60

CPC分类号： H01L24/83 ,  H01L21/4871 ,  H01L23/427 ,  H01L23/433 ,  H01L23/473 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/73253 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152

摘要： An electronic device includes an integrated circuit device, the integrated circuit device comprises a first substrate including an integrated electronic semiconductor circuit and a second substrate including a cooling accelerator for accelerating a heat energy exchange between the integrated electronic semiconductor circuit and a cooling fluid, and the second substrate is joined fixedly with the first substrate through a covalent bond formed between the first substrate and the second substrate.

摘要翻译： 电子设备包括集成电路器件，该集成电路器件包括包括集成电子半导体电路的第一衬底和包括用于加速集成电子半导体电路和冷却流体之间的热能交换的冷却加速器的第二衬底， 第二基板通过在第一基板和第二基板之间形成的共价键与第一基板固定连接。

公开(公告)号：US06330703B1

公开(公告)日：2001-12-11

申请号：US09041121

申请日：1998-03-12

申请人： Tatsuya Saito ,  Masayoshi Yagyu ,  Hiroki Yamashita ,  Tsuneyo Chiba ,  Masakazu Yamamoto

发明人： Tatsuya Saito ,  Masayoshi Yagyu ,  Hiroki Yamashita ,  Tsuneyo Chiba ,  Masakazu Yamamoto

IPC分类号： G06F1750

CPC分类号： G01R31/3004 ,  G06F2217/78

摘要： A logic circuit determines the power consumption of a semiconductor integrated device by taking into consideration the variation of the rate of operation. A control signal (TEST) is applied to each control signal input port (Tin) of flip-flop circuits of flip-flop circuit groups and a logic gate circuit having a plurality of input ports A and B in a combined circuit group. If the control signal (TEST) is low, both the flip-flop circuits and the logic gate circuit operate normally. However, if the control signal (TEST) is high, each of them performs the power consumption test. Regardless of the value of input signals applied to input ports D1 and D2 of the flip-flop circuits, the flip-flop circuits are controlled to have a repetitive output signal of high and low levels at ports Q1 and Q2, in synchronism with a clock signal. Through this operation test, operational failure is reduced and the quality of semiconductor chip production is guaranteed, because it is possible to predict accurately the power consumption when designing the logic circuit due to the relationship between the rate of operation and the power consumption.

摘要翻译： 逻辑电路通过考虑操作速率的变化来确定半导体集成器件的功耗。 控制信号（TEST）被施加到组合电路组中具有多个输入端口A和B的触发器电路组的触发器电路的每个控制信号输入端口（Tin）和逻辑门电路。 如果控制信号（TEST）低，触发器电路和逻辑门电路均正常工作。 但是，如果控制信号（TEST）为高，则进行功耗测试。 不管施加到触发器电路的输入端口D1和D2的输入信号的值如何，触发器电路被控制为具有在时钟Q1与Q2的端口Q1和Q2的高电平和低电平的重复输出信号 信号。 通过这种操作测试，可以降低运行故障，保证半导体芯片生产的质量，因为由于操作速率和功耗之间的关系，可以准确地预测设计逻辑电路时的功耗。

公开(公告)号：US4158883A

公开(公告)日：1979-06-19

申请号：US737350

申请日：1976-11-01

申请人： Shinji Kadono ,  Tsuneyo Chiba ,  Kiyoshi Umezawa

发明人： Shinji Kadono ,  Tsuneyo Chiba ,  Kiyoshi Umezawa

IPC分类号： G06F12/00 ,  G06F13/16 ,  G11C11/406 ,  G06F13/00 ,  G11C7/00

CPC分类号： G11C11/406 ,  G06F13/1636

摘要： In a refresh control system including a main memory having a volatile memory, at least one processing unit for accessing the main memory, a memory bus for effecting signal transfer between the main memory and the processing unit and a supervision circuit for allotting use of the memory bus in response to a request signal, the refresh control system is characterized by a refresh control circuit for transferring the request signal to the supervision circuit at the time the refresh signal is required and for commanding the initiation of the refresh operation to the main memory in response to a grant signal from the supervision circuit.

摘要翻译： 在包括具有易失性存储器的主存储器的刷新控制系统中，用于访问主存储器的至少一个处理单元，用于在主存储器和处理单元之间进行信号传送的存储器总线和用于分配存储器的使用的监控电路 总线响应于请求信号，刷新控制系统的特征在于刷新控制电路，用于在需要刷新信号时将请求信号传送到监控电路，并且用于命令向主存储器启动刷新操作 响应来自监控电路的授权信号。