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    Pattern inspection method and its apparatus
    3.
    发明授权
    Pattern inspection method and its apparatus 有权
    图案检验方法及其装置

    公开(公告)号：US07711178B2

    公开(公告)日：2010-05-04

    申请号：US11869217

    申请日：2007-10-09

    申请人： Kaoru Sakai ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    发明人： Kaoru Sakai ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T7/0002 ,  G06T7/32 ,  G06T7/33 ,  G06T2207/30148

    摘要： A pattern inspection method including: sequentially imaging plural chips formed on a substrate; selecting a pattern which is suitable for calculating position gap between an inspection image of a subject chip and reference image stored in memory from an image of a firstly imaged chip among said sequentially imaged plural chips formed on the substrate; computing position gap between an inspection image of a chip obtained by the sequential imaging and reference image stored in a memory by using a positional information of a pattern image included in the inspection image and a reference pattern image included in the reference image which are both corresponding to the pattern selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image and extracting a difference as a defect candidate.

    摘要翻译： 一种图案检查方法，包括：顺序成像形成在基板上的多个芯片; 从形成在所述基板上的所述顺序成像的多个芯片中，选择适合于计算被检体图像的检查图像与存储在存储器中的参考图像之间的位置间隔的图案， 通过使用包括在检查图像中的图案图像的位置信息和包括在参考图像中的参考图案图像来计算通过顺序成像获得的芯片的检查图像和存储在存储器中的参考图像之间的位置间隙， 到选择时选择的图案; 通过使用计算出的位置间隙的信息对准检查图像和参考图像; 并且将对准的检查图像与参考图像进行比较，并提取差异作为缺陷候选。

    Conductive porous layer for batteries and fabrication method for same
    4.
    发明授权
    Conductive porous layer for batteries and fabrication method for same 有权
    电池用导电性多孔层及其制造方法

    公开(公告)号：US09406940B2

    公开(公告)日：2016-08-02

    申请号：US14007423

    申请日：2012-03-23

    申请人： Naoya Takeuchi ,  Hiroshi Kishimoto ,  Kasumi Oi

    发明人： Naoya Takeuchi ,  Hiroshi Kishimoto ,  Kasumi Oi

    IPC分类号： H01M8/22 ,  H01M4/36 ,  B29C47/00 ,  H01M4/86 ,  H01M8/02 ,  H01M8/10 ,  H01M12/06 ,  H01M4/88 ,  H01M12/02

    CPC分类号： H01M4/8657 ,  H01M4/8605 ,  H01M4/8652 ,  H01M4/8668 ,  H01M4/8673 ,  H01M4/88 ,  H01M4/8875 ,  H01M8/0234 ,  H01M8/0239 ,  H01M8/0243 ,  H01M8/0245 ,  H01M8/1004 ,  H01M8/1007 ,  H01M12/02 ,  H01M12/06 ,  Y02E60/521 ,  Y02P70/56

    摘要： The conductive porous layer for batteries according to the present invention comprises a laminate comprising a first conductive layer and a second conductive layer. The first conductive layer includes at least a conductive carbon material and a polymer. The second conductive layer includes at least a conductive carbon material and a polymer. The conductive porous layer satisfies at least one of the following two conditions: “the polymer in the first conductive layer is present with a high density at the surface of the layer in contact with the second conductive layer than at the surface not in contact with the second conductive layer” and “the polymer in the second conductive layer is present with a higher density at the surface of the layer in contact with the first conductive layer than at the surface not in contact with the first conductive layer.”

    摘要翻译： 根据本发明的用于电池的导电多孔层包括包含第一导电层和第二导电层的层压体。 第一导电层至少包括导电碳材料和聚合物。 第二导电层至少包括导电碳材料和聚合物。 导电多孔层满足以下两个条件中的至少一个：“第一导电层中的聚合物在与第二导电层接触的层的表面处以比不与第二导电层接触的表面高密度存在 第二导电层“和”第二导电层中的聚合物在与第一导电层接触的层的表面处具有比在不与第一导电层接触的表面处更高的密度“。

    PATTERN INSPECTION METHOD AND ITS APPARATUS
    5.
    发明申请
    PATTERN INSPECTION METHOD AND ITS APPARATUS 审中-公开
    模式检验方法及其设备

    公开(公告)号：US20120076396A1

    公开(公告)日：2012-03-29

    申请号：US13312460

    申请日：2011-12-06

    申请人： Kaoru SAKAI ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    发明人： Kaoru SAKAI ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T7/0002 ,  G06T7/32 ,  G06T7/33 ,  G06T2207/30148

    摘要： A pattern inspection method and apparatus are provided for sequentially imaging plural chips formed on a substrate to be inspected to and obtaining inspection images and reference images, calculating a position gap between the inspection images and the reference images using a recipe created in advance by using another substrate of the same kind or type as the substrate, the recipe including information for determining which pattern sections are to be selected and discarded, aligning the inspection images and the reference images using information of the position gap from the calculating step, and comparing the inspection images with the reference images aligned by the aligning step and extracting a defect candidate.

    摘要翻译： 提供了一种图案检查方法和装置，用于将形成在要检查的基板上的多个芯片顺序地成像并获得检查图像和参考图像，使用预先通过使用另一个来创建的食谱来计算检查图像与参考图像之间的位置间隙 与基板相同种类或类型的基板，所述配方包括用于确定要选择和丢弃哪些图案部分的信息，使用来自计算步骤的位置间隙的信息对准检查图像和参考图像，并且将检查 具有通过对准步骤对齐的参考图像并提取缺陷候选的图像。

    PATTERN INSPECTION METHOD AND ITS APPARATUS
    6.
    发明申请
    PATTERN INSPECTION METHOD AND ITS APPARATUS 有权
    模式检验方法及其设备

    公开(公告)号：US20100172570A1

    公开(公告)日：2010-07-08

    申请号：US12725040

    申请日：2010-03-16

    申请人： Kaoru SAKAI ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    发明人： Kaoru SAKAI ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T7/0002 ,  G06T7/32 ,  G06T7/33 ,  G06T2207/30148

    摘要： A pattern inspection method including: sequentially imaging plural chip formed on a substrate; selecting at least one of pattern sections of each inspection image obtained by the imaging, while discarding other pattern sections, based on a recipe created in advance, the recipe including information for determining which pattern sections to be selected or discarded; calculating position gap between an inspection image of a chip obtained by the imaging and a reference image stored in a memory by using positional information of pattern images included in the inspection image and reference pattern images which are both corresponding to the at least one of pattern sections selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image, and extracting a difference between the two images as a defect candidate.

    摘要翻译： 一种图案检查方法，包括：顺序成像形成在基板上的多个芯片; 选择通过成像获得的每个检查图像的图案部分中的至少一个，同时基于预先创建的食谱来丢弃其他图案部分，所述配方包括用于确定要选择或丢弃的图案部分的信息; 通过使用包括在检查图像中的图案图像的位置信息和对应于图案部分中的至少一个的参考图案图像来计算通过成像获得的芯片的检查图像与存储在存储器中的参考图像之间的位置间隙 选择选择; 通过使用计算出的位置间隙的信息对准检查图像和参考图像; 以及将对准的检查图像与参考图像进行比较，并且将两个图像之间的差提取为缺陷候选。

    MEMBRANE-ELECTRODE ASSEMBLY FOR FUEL CELL, MANUFACTURING METHOD THEREOF, AND SOLID POLYMER FUEL CELL USING MEMBRANE-ELECTRODE ASSEMBLY
    7.
    发明申请
    MEMBRANE-ELECTRODE ASSEMBLY FOR FUEL CELL, MANUFACTURING METHOD THEREOF, AND SOLID POLYMER FUEL CELL USING MEMBRANE-ELECTRODE ASSEMBLY 审中-公开
    用于燃料电池的膜电极组件，其制造方法和使用膜电极组件的固体聚合物燃料电池

    公开(公告)号：US20140038077A1

    公开(公告)日：2014-02-06

    申请号：US14000076

    申请日：2012-02-17

    申请人： Naoya Takeuchi ,  Hiroshi Kishimoto

    发明人： Naoya Takeuchi ,  Hiroshi Kishimoto

    IPC分类号： H01M8/10

    CPC分类号： H01M8/1004 ,  H01M4/8642 ,  H01M4/881 ,  H01M8/0234 ,  H01M8/0239 ,  H01M8/0241 ,  H01M8/0243 ,  H01M8/0297 ,  H01M2008/1095 ,  Y02P70/56

    摘要： By stacking a gas diffusion layer, which comprises a first conductive layer comprising a specific conductive carbon material and a specific polymer, on a catalyst layer in such a manner that the first conductive layer is in contact with the catalyst layer and the polymer in the first conductive layer is present with a higher density at the surface of the layer in contact with the catalyst layer than at the surface not in contact with the catalyst layer, a membrane-electrode assembly having a strong adhesion between the catalyst layer and the gas diffusion layer can be provided. A fuel cell membrane-electrode assembly that reduces the position gap between a catalyst layer and a conductive porous layer, and between a conductive porous layer and a conductive porous substrate can be provided by using a gas diffusion layer that further comprises a second conductive layer formed on the first conductive layer.

    摘要翻译： 通过在催化剂层上堆叠包括由特定导电碳材料和特定聚合物构成的第一导电层的气体扩散层，使得第一导电层与第一导电层与第一导电层接触， 导电层在与催化剂层接触的层的表面处具有比在不与催化剂层接触的表面处具有更高的密度;在催化剂层和气体扩散层之间具有强粘附性的膜 - 电极组件 可以提供。 可以通过使用进一步包括形成的第二导电层的气体扩散层来提供减少催化剂层和导电多孔层之间以及导电多孔层和导电多孔基材之间的位置间隙的燃料电池膜 - 电极组件 在第一导电层上。

    PATTERN INSPECTION METHOD AND ITS APPARATUS
    8.
    发明申请
    PATTERN INSPECTION METHOD AND ITS APPARATUS 有权
    模式检验方法及其设备

    公开(公告)号：US20080031511A1

    公开(公告)日：2008-02-07

    申请号：US11869217

    申请日：2007-10-09

    申请人： Kaoru Sakai ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    发明人： Kaoru Sakai ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T7/0002 ,  G06T7/32 ,  G06T7/33 ,  G06T2207/30148

    摘要： A pattern inspection method including: sequentially imaging plural chips formed on a substrate; selecting a pattern which is suitable for calculating position gap between an inspection image of a subject chip and reference image stored in memory from an image of a firstly imaged chip among said sequentially imaged plural chips formed on the substrate; computing position gap between an inspection image of a chip obtained by the sequential imaging and reference image stored in a memory by using a positional information of a pattern image included in the inspection image and a reference pattern image included in the reference image which are both corresponding to the pattern selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image and extracting a difference as a defect candidate.

    摘要翻译： 一种图案检查方法，包括：顺序成像形成在基板上的多个芯片; 从形成在所述基板上的所述顺序成像的多个芯片中，选择适合于计算被检体图像的检查图像与存储在存储器中的参考图像之间的位置间隔的图案， 通过使用包括在检查图像中的图案图像的位置信息和包括在参考图像中的参考图案图像来计算通过顺序成像获得的芯片的检查图像和存储在存储器中的参考图像之间的位置间隙， 到选择时选择的图案; 通过使用计算出的位置间隙的信息对准检查图像和参考图像; 并且将对准的检查图像与参考图像进行比较，并提取差异作为缺陷候选。

    CONDUCTIVE POROUS LAYER FOR BATTERIES AND FABRICATION METHOD FOR SAME
    9.
    发明申请
    CONDUCTIVE POROUS LAYER FOR BATTERIES AND FABRICATION METHOD FOR SAME 有权
    导电多孔电池和制造方法

    公开(公告)号：US20140087272A1

    公开(公告)日：2014-03-27

    申请号：US14007423

    申请日：2012-03-23

    申请人： Naoya Takeuchi ,  Hiroshi Kishimoto ,  Kasumi Oi

    发明人： Naoya Takeuchi ,  Hiroshi Kishimoto ,  Kasumi Oi

    IPC分类号： H01M4/86 ,  H01M4/88 ,  H01M12/02

    CPC分类号： H01M4/8657 ,  H01M4/8605 ,  H01M4/8652 ,  H01M4/8668 ,  H01M4/8673 ,  H01M4/88 ,  H01M4/8875 ,  H01M8/0234 ,  H01M8/0239 ,  H01M8/0243 ,  H01M8/0245 ,  H01M8/1004 ,  H01M8/1007 ,  H01M12/02 ,  H01M12/06 ,  Y02E60/521 ,  Y02P70/56

    摘要： The conductive porous layer for batteries according to the present invention comprises a laminate comprising a first conductive layer and a second conductive layer. The first conductive layer includes at least a conductive carbon material and a polymer. The second conductive layer includes at least a conductive carbon material and a polymer. The conductive porous layer satisfies at least one of the following two conditions: “the polymer in the first conductive layer is present with a high density at the surface of the layer in contact with the second conductive layer than at the surface not in contact with the second conductive layer” and “the polymer in the second conductive layer is present with a higher density at the surface of the layer in contact with the first conductive layer than at the surface not in contact with the first conductive layer.”

    摘要翻译： 根据本发明的用于电池的导电多孔层包括包含第一导电层和第二导电层的层压体。 第一导电层至少包括导电碳材料和聚合物。 第二导电层至少包括导电碳材料和聚合物。 导电多孔层满足以下两个条件中的至少一个：“第一导电层中的聚合物在与第二导电层接触的层的表面处以比不与第二导电层接触的表面高密度存在 第二导电层“和”第二导电层中的聚合物在与第一导电层接触的层的表面处具有比在不与第一导电层接触的表面处更高的密度“。

    Pattern inspection method and its apparatus
    10.
    发明授权
    Pattern inspection method and its apparatus 有权
    图案检验方法及其装置

    公开(公告)号：US08090187B2

    公开(公告)日：2012-01-03

    申请号：US12725040

    申请日：2010-03-16

    申请人： Kaoru Sakai ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    发明人： Kaoru Sakai ,  Shunji Maeda ,  Takafumi Okabe ,  Hiroshi Goto ,  Masayuki Kuwabara ,  Naoya Takeuchi

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T7/0002 ,  G06T7/32 ,  G06T7/33 ,  G06T2207/30148

    摘要： A pattern inspection method including: sequentially imaging plural chip formed on a substrate; selecting at least one of pattern sections of each inspection image obtained by the imaging, while discarding other pattern sections, based on a recipe created in advance, the recipe including information for determining which pattern sections to be selected or discarded; calculating position gap between an inspection image of a chip obtained by the imaging and a reference image stored in a memory by using positional information of pattern images included in the inspection image and reference pattern images which are both corresponding to the at least one of pattern sections selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image, and extracting a difference between the two images as a defect candidate.

    摘要翻译： 一种图案检查方法，包括：顺序成像形成在基板上的多个芯片; 选择通过成像获得的每个检查图像的图案部分中的至少一个，同时基于预先创建的食谱来丢弃其他图案部分，所述配方包括用于确定要选择或丢弃的图案部分的信息; 通过使用包括在检查图像中的图案图像的位置信息和对应于图案部分中的至少一个的参考图案图像来计算通过成像获得的芯片的检查图像与存储在存储器中的参考图像之间的位置间隙 选择选择; 通过使用计算出的位置间隙的信息对准检查图像和参考图像; 以及将对准的检查图像与参考图像进行比较，并且将两个图像之间的差提取为缺陷候选。