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    SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR 有权
    半导体器件和场效应晶体管

    公开(公告)号：US20130113028A2

    公开(公告)日：2013-05-09

    申请号：US13393002

    申请日：2010-06-23

    申请人： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA ,  Kazuomi ENDO

    发明人： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA ,  Kazuomi ENDO

    IPC分类号： H01L29/78

    CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

    摘要： A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

    摘要翻译： 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

    DATA STORAGE APPARATUS, MEMORY CONTROL METHOD AND ELECTRONIC DEVICE WITH DATA STORAGE APPARATUS
    3.
    发明申请
    DATA STORAGE APPARATUS, MEMORY CONTROL METHOD AND ELECTRONIC DEVICE WITH DATA STORAGE APPARATUS 审中-公开
    数据存储设备，存储器控制方法和具有数据存储设备的电子设备

    公开(公告)号：US20140032820A1

    公开(公告)日：2014-01-30

    申请号：US13723958

    申请日：2012-12-21

    申请人： Akinori HARASAWA ,  Yoko MASUO ,  Hironobu MIYAMOTO

    发明人： Akinori HARASAWA ,  Yoko MASUO ,  Hironobu MIYAMOTO

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7205

    摘要： According to one embodiment, a data storage apparatus comprises a first controller, a second controller, and a third controller. The first controller controls first write processing of writing data to a flash memory in accordance with a request from a host. The second controller controls second write processing of writing data to the flash memory, the second write processing is different from the first write processing.

    摘要翻译： 根据一个实施例，数据存储装置包括第一控制器，第二控制器和第三控制器。 第一控制器控制根据来自主机的请求向闪存写入数据的第一写入处理。 第二控制器控制向闪存写入数据的第二写入处理，第二写入处理与第一写入处理不同。

    MEMORY SYSTEM AND MANAGING METHOD THEREFOR
    4.
    发明申请
    MEMORY SYSTEM AND MANAGING METHOD THEREFOR 有权
    存储系统及其管理方法

    公开(公告)号：US20100205391A1

    公开(公告)日：2010-08-12

    申请号：US12563624

    申请日：2009-09-21

    申请人： Hironobu MIYAMOTO

    发明人： Hironobu MIYAMOTO

    IPC分类号： G06F12/16 ,  G06F12/00

    CPC分类号： G06F11/1441 ,  G06F11/008 ,  G06F11/1471 ,  G06F2201/84

    摘要： A memory system in which a first management unit includes an update information managing unit that manages update information indicating an updated section in status information stored in a volatile first storing unit, and an update information notifying unit that notifies a second management unit of the update information managed by the update information managing unit, and the second management unit includes a commit executing unit that collects, based on the update information, difference information of the status information from the status area when the update information is notified from the update information notifying unit, and causes a second storing unit to accumulate the difference information in a backup area.

    摘要翻译： 一种存储系统，其中第一管理单元包括更新信息管理单元，其管理存储在易失性第一存储单元中的状态信息中指示更新部分的更新信息;以及更新信息通知单元，其向第二管理单元通知更新信息 并且所述第二管理单元包括提交执行单元，当所述更新信息通知单元通知所述更新信息时，所述提交执行单元基于所述更新信息从所述状态区域收集所述状态信息的差异信息， 并且使第二存储单元将差分信息累积在备份区域中。

    MEMORY SYSTEM
    5.
    发明申请
    MEMORY SYSTEM 有权
    记忆系统

    公开(公告)号：US20100205353A1

    公开(公告)日：2010-08-12

    申请号：US12559983

    申请日：2009-09-15

    申请人： Hironobu MIYAMOTO ,  Hajime Yamazaki ,  Shinji Yonezawa

    发明人： Hironobu MIYAMOTO ,  Hajime Yamazaki ,  Shinji Yonezawa

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F12/0246 ,  G06F11/1471 ,  G06F2201/84 ,  G06F2212/7201

    摘要： A memory system according to an embodiment of the present invention comprises: a log overflow control unit that, when a third condition in which a second log accumulated in a log storage area exceeds a set value is satisfied, stops a recording operation of the second log in the log storage area by a log recording unit and causes a log recording unit to perform an update operation of a second management table in a master table and a recording operation of a first log in the log storage area, and that, when a first condition is satisfied next time, prohibits a commit operation by a log reflecting unit and causes a snapshot storing unit to perform a snapshot storing operation.

    摘要翻译： 根据本发明实施例的存储器系统包括：日志溢出控制单元，当满足累积在日志存储区域中的第二对数超过设定值的第三条件时，停止第二日志的记录操作 在日志记录单元的日志存储区域中，使日志记录单元执行主表中的第二管理表的更新操作和日志存储区中的第一日志的记录操作，并且当第一 条件下一次被满足时，禁止日志反射单元的提交操作，并使快照存储单元执行快照存储操作。