公开(公告)号：US20190051742A1

公开(公告)日：2019-02-14

申请号：US16153037

申请日：2018-10-05

Applicant: Infineon Technologies Austria AG

Inventor： Andreas Riegler ,  Christian Fachmann ,  Gabor Mezoesi ,  Hans Weber

IPC: H01L29/78 ,  H01L23/31 ,  H01L23/495 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L29/0634 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/304 ,  H01L21/324 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A semiconductor device includes an electrically conductive lead frame which includes a die pad and a plurality of electrically conductive leads, each of the leads in the plurality being spaced apart from the die pad. The semiconductor device further includes first and second integrated switching devices mounted on the die pad, each of the first and second integrated switching devices include electrically conductive gate, source and drain terminals. The source terminal of the first integrated switching device is disposed on a rear surface of the first integrated switching device that faces and electrically connects with the die pad. The drain terminal of the second integrated switching device is disposed on a rear surface of the second integrated switching device that faces and electrically connects with the die pad.

公开(公告)号：US10079230B2

公开(公告)日：2018-09-18

申请号：US15240009

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber ,  Stuart B. Molin

IPC: H01L29/66 ,  H01L27/082 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L27/088 ,  H01L29/06 ,  H01L21/683 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L23/00

CPC classification number: H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

公开(公告)号：US20180053822A1

公开(公告)日：2018-02-22

申请号：US15675913

申请日：2017-08-14

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Anton Mauder

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/02 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0649 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/31144 ,  H01L27/0629 ,  H01L27/1207 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7812 ,  H01L29/7813

Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.

公开(公告)号：US09831334B2

公开(公告)日：2017-11-28

申请号：US15198526

申请日：2016-06-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. Loechelt

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/7809 ,  H01L21/28132 ,  H01L29/063 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813

Abstract: An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.

公开(公告)号：US09673219B2

公开(公告)日：2017-06-06

申请号：US14576122

申请日：2014-12-18

Applicant: QUALCOMM Incorporated

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L29/78 ,  H01L21/683 ,  H01L21/84 ,  H01L29/73 ,  H01L23/00 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/823487 ,  H01L21/84 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

公开(公告)号：US20160211348A1

公开(公告)日：2016-07-21

申请号：US14601242

申请日：2015-01-21

Applicant: Maxchip Electronics Corp.

Inventor： Kosuke Yoshida

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/823456 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7809 ,  H01L29/7812

Abstract: A trench lateral diffusion metal oxide semiconductor (LDMOS) device, disposed on a substrate, comprising: a transistor and an LDMOS transistor. The transistor has a gate. The LDMOS transistor has a trench gate, wherein the trench gate protrudes from a surface of the substrate. Electrical connection of the trench gate and a doping region due to a metal silicide may be prevented by protruding the trench gate from the surface of the substrate. And furthermore a step height difference between a gate and the trench gate may be decreased, and openings respectively exposing a top portion of the trench gate and a top portion of the gate may be formed without changing the manufacturing conditions.

Abstract translation: 设置在基板上的沟槽横向扩散金属氧化物半导体（LDMOS）器件，包括：晶体管和LDMOS晶体管。 晶体管有一个门。 LDMOS晶体管具有沟槽栅极，其中沟槽栅极从衬底的表面突出。 通过从衬底的表面突出沟槽栅极可以防止由于金属硅化物引起的沟槽栅极和掺杂区域的电连接。 此外，可以减小栅极和沟槽栅极之间的台阶高度差，并且可以在不改变制造条件的情况下形成分别暴露沟槽栅极的顶部和栅极顶部的开口。

公开(公告)号：US09136158B2

公开(公告)日：2015-09-15

申请号：US13415965

申请日：2012-03-09

Applicant: Po-Yu Chen

Inventor： Po-Yu Chen

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7809 ,  H01L21/26513 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/78642

Abstract: A lateral trench MOSFET comprises a dielectric isolation trench formed over a silicon-on-insulator substrate. The lateral trench MOSFET further comprises a first drift region formed between a drain/source region and an insulator, and a second drift region formed between the dielectric isolation trench and the insulator. The dielectric trench and the insulator help to fully deplete the drift regions. The depleted regions can improve the breakdown voltage as well as the on-resistance of the lateral trench MOSFET.

Abstract translation: 横向沟槽MOSFET包括在绝缘体上硅衬底上形成的介质隔离沟槽。 横向沟槽MOSFET还包括形成在漏极/源极区域和绝缘体之间的第一漂移区域和形成在介电隔离沟槽和绝缘体之间的第二漂移区域。 电介质沟槽和绝缘子有助于完全耗尽漂移区域。 耗尽区可以提高击穿电压以及横向沟槽MOSFET的导通电阻。

公开(公告)号：US20150069503A1

公开(公告)日：2015-03-12

申请号：US14025416

申请日：2013-09-12

Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

Inventor： Hsiung-Shih CHANG ,  Jui-Chun CHANG

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/402 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7828

Abstract: A semiconductor device including a substrate having an active region is disclosed. A field-plate region and a bulk region are in the active region, wherein the bulk region is at a first side of the field-plate region. At least one trench-gate structure is disposed in the substrate corresponding to the bulk region. At least one source-doped region is in the substrate corresponding to the bulk region, wherein the source-doped region surrounds the trench-gate structure. A drain-doped region is in the substrate at a second side opposite to the first side of the field-plate region, wherein an extending direction of length of the trench-gate structure is perpendicular to that of the drain-doped region as viewed from a top view perspective.

Abstract translation: 公开了一种包括具有有源区的衬底的半导体器件。 场板区域和体区域处于有源区域中，其中本体区域位于场板区域的第一侧。 至少一个沟槽栅极结构设置在对应于本体区域的衬底中。 至少一个源极掺杂区域在与衬底区域对应的衬底中，其中源极掺杂区域围绕沟槽栅极结构。 漏极掺杂区域在与场板区域的第一侧相对的第二侧的衬底中，其中沟槽栅极结构的延伸方向垂直于漏极掺杂区域的延伸方向，如从 顶视图。

公开(公告)号：US08921945B2

公开(公告)日：2014-12-30

申请号：US12999028

申请日：2009-06-15

Applicant: Ralf Lerner

Inventor： Ralf Lerner

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7394 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/7803 ,  H01L29/7812

Abstract: The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 μm. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.

Abstract translation: 功率晶体管被配置为集成到具有约50μm的厚度的活性硅层的沟槽隔离厚层SOI技术中。 功率晶体管可能具有比DMOS晶体管更低的电阻，并且具有比IGBT更快的关断特性。

公开(公告)号：US20140252466A1

公开(公告)日：2014-09-11

申请号：US13794020

申请日：2013-03-11

Applicant: Gary H. Loechelt

Inventor： Gary H. Loechelt

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7809 ,  H01L21/28132 ,  H01L29/063 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813

Abstract: An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.

Abstract translation: 电子器件可以包括半导体层，覆盖半导体层的绝缘层和导电电极。 在一个实施例中，第一导电电极部件覆盖绝缘层，并且第二导电电极部件覆盖并与半导体层间隔开。 第二导电电极构件具有与第一端相对的第一端和第二端，其中半导体层和第一导电电极构件中的每一个比第二导电电极构件的第二端更靠近第二导电电极构件的第一端 导电电极部件。 在另一个实施例中，导电电极可以是大致L形的。 在另一实施例中，工艺可以包括形成第一和第二导电电极部件，使得它们彼此邻接。 第二导电电极部件可以具有侧壁间隔物的形状。