公开(公告)号：US20060064546A1

公开(公告)日：2006-03-23

申请号：US11190004

申请日：2005-07-27

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Koutaro Shimamura ,  Yasuwo Watanabe

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Koutaro Shimamura ,  Yasuwo Watanabe

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/3824

摘要： [Problem] To provide a microprocessor in which the bottleneck due to data sharing during memory access when a CPU and a plurality of accelerators are operated in a linked up manner can be minimized, whereby enhanced multimedia processing performance can be achieved. [Means for solving the problem] A multimedia microprocessor 1 includes a CPU 11 and accelerators 12 in which the CPU 11 and the accelerators 12 perform multimedia processing in a linked up manner. In order to prevent the bottleneck caused by data sharing during memory access between the CPU 11 and the accelerators 12 via a memory 2, an I/O dedicated cache 14 is provided in front of the memory 2 to which the CPU 11 and the accelerators 12 can commonly access. Data required for data sharing is stored in the I/O dedicated cache 14, whereby data sharing between the CPU 11 and the accelerators 12 can be performed at higher speed and the speed of multimedia processing can be increased.

摘要翻译： [问题]提供一种微处理器，其中当CPU和多个加速器以连接的方式操作时，由于在存储器访问期间的数据共享造成的瓶颈可以被最小化，从而可以实现增强的多媒体处理性能。

公开(公告)号：US07428690B2

公开(公告)日：2008-09-23

申请号：US10921879

申请日：2004-08-20

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

IPC分类号： G11C29/00

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L69/161 ,  H04L69/162 ,  H04L69/22

摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

公开(公告)号：US07814223B2

公开(公告)日：2010-10-12

申请号：US12010762

申请日：2008-01-29

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

IPC分类号： G06F13/00

CPC分类号： H04L47/6255 ,  H04L12/44 ,  H04L47/10 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/522 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/351

摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

摘要翻译： 由CPU1生成的发送包被保存在缓冲器100a（100b）中。 从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。 应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。 如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。 如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于 传输分组的传输分组优先于传送分组传送到以太网820a或820b。 这防止了传送缓冲器装置溢出。

公开(公告)号：US07496679B2

公开(公告)日：2009-02-24

申请号：US10446929

申请日：2003-05-29

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Yoshihiro Tanaka ,  Kenji Furuhashi

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Yoshihiro Tanaka ,  Kenji Furuhashi

IPC分类号： G06F15/16

CPC分类号： H04L29/06 ,  H04L49/90 ,  H04L69/08

摘要： A packet communication apparatus capable of performing packet conversion at high speed for packet transfer or packet transmission/reception has: a packet conversion unit for performing packet conversion for a reception packet received at a plurality of communication units and for a transmission packet to be transmitted from the plurality of communication units; and a transfer control unit for outputting, when the reception packet received by the communication unit is judged as a the transfer packet, the reception packet to a transfer buffer, for outputting the transmission packet to the communication unit corresponding to the communication object at a destination of the transmission packet generated by a packet generating and processing unit, and for outputting the transfer packet to the communication unit corresponding to the communication object at a destination of the transfer packet stored in the transfer buffer.

摘要翻译： 能够高速进行分组转换以进行分组传送或分组发送/接收的分组通信装置具有：分组转换单元，用于对在多个通信单元接收的接收分组进行分组转换，以及对于要从 所述多个通信单元; 以及传送控制单元，用于当将由通信单元接收到的接收分组判断为传送分组时，将接收分组输出到传送缓冲器，用于将发送分组输出到与目的地的通信对象相对应的通信单元 由分组产生和处理单元产生的传输分组，并且用于将存储在传送缓冲器中的传送分组的目的地处的传送分组输出到与通信对象对应的通信单元。

公开(公告)号：US20110096667A1

公开(公告)日：2011-04-28

申请号：US12873893

申请日：2010-09-01

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

IPC分类号： H04L12/28 ,  H04L12/26

CPC分类号： H04L47/6255 ,  H04L12/44 ,  H04L47/10 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/522 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/351

摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

摘要翻译： 由CPU1生成的发送包被保存在缓冲器100a（100b）中。 从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。 应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。 如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。 如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于 传输分组的传输分组优先于传送分组传送到以太网820a或820b。 这防止了传送缓冲器装置溢出。

公开(公告)号：US20050068897A1

公开(公告)日：2005-03-31

申请号：US10921879

申请日：2004-08-20

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

IPC分类号： H04L12/70 ,  G06F13/00 ,  H04L1/00 ,  H04L29/06 ,  H04M11/00

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L69/161 ,  H04L69/162 ,  H04L69/22

摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

摘要翻译： 包括CPU，存储器和分组通信电路的分组通信装置充当远程监视和控制受控对象的网络连接受控对象和网络终端之间的接口，并且在 受控对象和网络终端还包括作为用于执行校验和计算以检查分组错误和复制操作的硬件单元的复制和操作单元。 复制和操作单元在存储器中形成并由分组通信电路使用的发送缓冲器/接收缓冲器与由通信处理程序使用的工作区域之间同时执行分组数据复制操作和校验和计算，从而减少 加载CPU并增加通信处理速度。

公开(公告)号：US08423661B2

公开(公告)日：2013-04-16

申请号：US12873893

申请日：2010-09-01

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

IPC分类号： G06F13/00

CPC分类号： H04L47/6255 ,  H04L12/44 ,  H04L47/10 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/522 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/351

摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

公开(公告)号：US20080177855A1

公开(公告)日：2008-07-24

申请号：US12076686

申请日：2008-03-21

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

IPC分类号： G06F15/16

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L69/161 ,  H04L69/162 ,  H04L69/22

摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

摘要翻译： 包括CPU，存储器和分组通信电路的分组通信装置充当远程监视和控制受控对象的网络连接受控对象和网络终端之间的接口，并且在 受控对象和网络终端还包括作为用于执行校验和计算以检查分组错误和复制操作的硬件单元的复制和操作单元。 复制和操作单元在存储器中形成并由分组通信电路使用的发送缓冲器/接收缓冲器与由通信处理程序使用的工作区域之间同时执行分组数据复制操作和校验和计算，从而减少 加载CPU并增加通信处理速度。

公开(公告)号：US20070250184A1

公开(公告)日：2007-10-25

申请号：US11737850

申请日：2007-04-20

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka

IPC分类号： G05B13/02

CPC分类号： G05B13/024 ,  G05B15/02 ,  G06Q10/04 ,  G06Q50/06

摘要： An optimizing control system includes at least a local control unit for controlling at least a control apparatus, an integration control apparatus for controlling a plurality of the local control units in integration fashion, and at least a control information standardization interface arranged between the local control unit and the integration control apparatus for standardizing the control information transmitted and received between the local control unit 31 and the integration control apparatus. The control information standardization interface includes a control condition information storage unit for storing the constraints, the evaluation function and the attribute information expressed by a predetermined standard physical quantity for controlling the local apparatus, and a physical quantity converter for converting the local physical status amount acquired from the local apparatus into a standard physical status amount and converting the optical setpoint calculated by the integration control apparatus into a local control goal value.

摘要翻译： 一种优化控制系统至少包括用于至少控制控制装置的本地控制单元，用于以集成方式控制多个本地控制单元的集成控制装置，以及布置在本地控制单元之间的控制信息标准化接口 以及用于使本地控制单元31和积分控制装置之间发送和接收的控制信息标准化的积分控制装置。 控制信息标准化接口包括：控制条件信息存储单元，用于存储用于控制本地设备的预定标准物理量表示的约束，评估功能和属性信息;以及物理量转换器，用于转换所获取的本地物理状态量 从本地装置进入标准物理状态量，并将由积分控制装置计算出的光学设定值转换为本地控制目标值。

公开(公告)号：US20090092147A1

公开(公告)日：2009-04-09

申请号：US12010762

申请日：2008-01-29

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Tasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Tasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

IPC分类号： H04L12/28

CPC分类号： H04L47/6255 ,  H04L12/44 ,  H04L47/10 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/522 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/351

摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

摘要翻译： 由CPU1生成的发送包被保存在缓冲器100a（100b）中。 从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。 应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。 如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。 如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于 传输分组的传输分组优先于传送分组传送到以太网820a或820b。 这防止了传送缓冲器装置溢出。