Optical time domain reflectometer using optical element with three
control modes of oscillation, attenuation and amplification
    1.
    发明授权
    Optical time domain reflectometer using optical element with three control modes of oscillation, attenuation and amplification 失效
    光时域反射仪采用光学元件,具有三种控制模式的振荡,衰减和放大

    公开(公告)号:US5028775A

    公开(公告)日:1991-07-02

    申请号:US543971

    申请日:1990-06-26

    IPC分类号: G01M11/00 G01M11/02

    CPC分类号: G01M11/3109 G01M11/319

    摘要: An optical element has three operation modes of light oscillation, light amplification, and light attenuation, which are switched in accordance with the intensity of an excitation component. The optical element having a first light terminal from which a light pulse is output to an optical fiber to be tested, and a second light terminal through which reflected light from the optical fiber is passed in the amplification mode or in the attenuation mode. Light-receiving section receives the reflected light output from the second light terminal of the optical element, and converts the reflected light into an electric signal. Signal processing section subjects the electric signal output from the light-receiving section to a predetermined signal processing step for testing the optical fiber. Excitation component control section outputs to the optical element a first excitation component for enabling the optical element to operate in the oscillation mode at a first timing, a second excitation component for enabling the optical element to operate in the attenuation mode at a second timing subsequent to the first timing, and a third excitation component for enabling the optical element to operate in the amplification mode at a third timing subsequent to the second timing.

    PHYSICAL QUANTITY MEASURING SYSTEM AND PHYSICAL QUANTITY MEASURING METHOD
    2.
    发明申请
    PHYSICAL QUANTITY MEASURING SYSTEM AND PHYSICAL QUANTITY MEASURING METHOD 审中-公开
    物理量测量系统和物理量测量方法

    公开(公告)号:US20150036134A1

    公开(公告)日:2015-02-05

    申请号:US14447868

    申请日:2014-07-31

    IPC分类号: G01N21/25 G02B6/293

    摘要: A physical quantity measuring system includes an optical source which emits a measurement light to fiber Bragg grating (FBG) lines containing FBGs connected in cascade by an optical fiber, an optical switch including a common port for receiving the measurement light from the optical source, and input/output ports connected to the FBG lines, the optical switch outputting the measurement light, from the common port to each of the input/output ports at different time points, a wavelength separator which receives light reflected from the respective FBGs of the FBG lines, and separating the reflected light into a plurality of component lights having predetermined wavelengths, after the measurement light is output from the input/output ports, and optical receivers which receives the component lights from the wavelength separator and detects light intensities of the component lights.

    摘要翻译: 物理量测量系统包括:光源,其向包含由光纤串联连接的FBG的光纤布拉格光栅(FBG)线发射测量光;光开关,包括用于接收来自光源的测量光的公共端口;以及 连接到FBG线的输入/输出端口,光学开关将不同时间点的公共端口从公共端口输出到每个输入/输出端口;波长分离器,其接收从FBG线的各个FBG反射的光 并且在从输入/输出端口输出测量光和从波长分离器接收分量光的光接收器之后,将反射光分离成具有预定波长的多个分量光,并检测分量光的光强度。

    Connection method, connection tool, and connection jig for optical fiber
    3.
    发明授权
    Connection method, connection tool, and connection jig for optical fiber 有权
    光纤连接方法,连接工具和连接夹具

    公开(公告)号:US08480314B2

    公开(公告)日:2013-07-09

    申请号:US12965377

    申请日:2010-12-10

    IPC分类号: G02B6/255

    摘要: A method of butting and connecting a first optical fiber and a second optical fiber in an optical connector comprises placing said optical connector that holds said first optical fiber in wherein an optical fiber connection tool; mounting said optical fiber holder on a holder mounting base of a front end bevel processing tool; processing a front end face of said second optical fiber such that said front end face of said second optical fiber is beveled relative to the surface perpendicular to the optical fiber axis direction; transferring said optical fiber holder to said holder support base; and moving said optical fiber holder toward said optical connector along said guide part, and butting and connecting the beveled front end face of said second optical fiber to the front end face of said first optical fiber such that their bevel directions are aligned.

    摘要翻译: 一种在光连接器中对接和连接第一光纤和第二光纤的方法包括将保持所述第一光纤的所述光连接器放置在其中的光纤连接工具; 将所述光纤保持器安装在前端斜面加工工具的保持器安装基座上; 处理所述第二光纤的前端面,使得所述第二光纤的所述前端面相对于垂直于所述光纤轴线方向的表面倾斜; 将所述光纤保持器传送到所述保持器支撑基座; 以及沿着所述引导部件将所述光纤保持器朝着所述光连接器移动,并且将所述第二光纤的斜面前端面对接并连接到所述第一光纤的前端面,使得它们的斜面方向对齐。

    Semiconductor integrated circuit in in a carry computation network having a logic blocks which are dynamically reconfigurable
    4.
    发明授权
    Semiconductor integrated circuit in in a carry computation network having a logic blocks which are dynamically reconfigurable 有权
    携带计算网络中的半导体集成电路具有可动态重新配置的逻辑块

    公开(公告)号:US08352533B2

    公开(公告)日:2013-01-08

    申请号:US12332673

    申请日:2008-12-11

    申请人: Hiroshi Furukawa

    发明人: Hiroshi Furukawa

    IPC分类号: G06F7/57

    CPC分类号: G06F7/5443

    摘要: There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner.

    摘要翻译: 提供了一种半导体集成电路,包括:多个可重新配置的第一逻辑块,多个第一逻辑块输入第一位宽的数据并执行计算; 以动态可重新配置的方式连接所述多个第一逻辑块的第一网络; 多个第二逻辑块,输入与第一位宽不同的第二位宽的数据,并执行计算; 连接到所述多个第二逻辑块的输出的第二网络; 以及以动态可重新配置的方式将包括在第一逻辑块中的计算单元的进位位输出连接到包括在第二逻辑块中的计算单元的输入的第三网络。

    COMMUNICATION SYSTEM, A SLAVE NODE, A ROUTE MAKING METHOD AND A PROGRAM
    5.
    发明申请
    COMMUNICATION SYSTEM, A SLAVE NODE, A ROUTE MAKING METHOD AND A PROGRAM 有权
    通信系统,从站节点,路由制作方法和程序

    公开(公告)号:US20120320781A1

    公开(公告)日:2012-12-20

    申请号:US13580816

    申请日:2011-02-23

    IPC分类号: H04W40/02 H04W24/00

    摘要: Provided are a communication system and the like capable of making a stable relay route even when a propagation channel is fluctuated by the fluctuation of RSSI. For making a tree-type communication route whose root is a core node, each slave node, after the reception of the latest reset routing packet from a node, judges if the transmission source node should be the parent of the tree-type structure based on the sequential average of the reception power of n routing packets received from the same transmission source node. As the reception power is log-normally distributed in general, an asymptotically stable relay route can be obtained, especially by using the sequential average.

    摘要翻译: 即使当传播路径由于RSSI的波动而波动时,也能够进行稳定的中继路径的通信系统等。 为了制作其根为核心节点的树型通信路由,每个从节点在从节点接收到最新的重置路由分组后,根据以下情况判断传输源节点是否为树型结构的父节点 从同一发送源节点接收的n个路由分组的接收功率的顺序平均值。 由于接收功率一般是对数正态分布的,所以可以获得渐近稳定的中继路由,特别是通过使用顺序平均值。

    Enhanced processor element structure in a reconfigurable integrated circuit device
    6.
    发明授权
    Enhanced processor element structure in a reconfigurable integrated circuit device 有权
    可重构集成电路设备中增强的处理器元件结构

    公开(公告)号:US07734896B2

    公开(公告)日:2010-06-08

    申请号:US11390131

    申请日:2006-03-28

    申请人: Hiroshi Furukawa

    发明人: Hiroshi Furukawa

    IPC分类号: G06F15/76

    CPC分类号: G06F15/8007

    摘要: A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.

    摘要翻译: 基于配置数据动态地转换任意计算状态的可重构集成电路装置包括多个处理器元件,每个处理器元件具有输入端子,输出端子,并行设置的多个运算单元, 其执行与时钟信号同步的计算处理和以任意状态连接它们的处理器内网络; 以及以任意状态连接处理器元件之间的处理器间网络。 基于配置数据,内部处理器网络可重新配置为期望的连接状态,并且此外,基于配置数据,处理器间网络可重新配置为期望的连接状态。

    Optical connector
    9.
    发明授权

    公开(公告)号:US07452138B2

    公开(公告)日:2008-11-18

    申请号:US11527564

    申请日:2006-09-27

    IPC分类号: G02B6/36

    CPC分类号: G02B6/3846

    摘要: An optical connector includes a connector body that has a first optical fiber housed in advance in a ferrule so as to project from a back end of the ferrule opposite to the connecting end surface and an anchoring fixture that anchors a second optical fiber that is to be optically connected to the first optical fiber, and by pressing the anchoring fixture into the connector body while the second optical fiber is anchored in this anchoring fixture, the anchoring fixture and the connector body are connected to optically connect the first optical fiber and the second optical fiber, and the connecting portion that connects the anchoring fixture and the connector body form a movable connecting portion that is adapted to vary the direction of the anchoring fixture with respect to the connector body.

    PROCESSING ELEMENT AND RECONFIGURABLE CIRCUIT INCLUDING THE SAME
    10.
    发明申请
    PROCESSING ELEMENT AND RECONFIGURABLE CIRCUIT INCLUDING THE SAME 审中-公开
    处理元件和可重新组合的电路,包括它们

    公开(公告)号:US20080205582A1

    公开(公告)日:2008-08-28

    申请号:US12033969

    申请日:2008-02-20

    申请人: Hiroshi Furukawa

    发明人: Hiroshi Furukawa

    IPC分类号: G11C19/00

    CPC分类号: G11C19/00 H03K19/17728

    摘要: A processing element includes a shift register including n stages of registers mutually connected in series. Data held among the n stages of registers is rotated in synchronization with a clock signal. A number-of-stages determining circuit determines the number of stages to be used among the n stages of registers. An output terminal of the register in the last stage connects to an input terminal of the register in the first stage.

    摘要翻译: 一种处理元件包括一个移位寄存器,它包括串联相互连接的n级寄存器。 在n个寄存器之间保存的数据与时钟信号同步旋转。 级数确定电路确定在n级寄存器中要使用的级数。 最后一级寄存器的输出端子连接到第一级寄存器的输入端。