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    Nonvolatile semiconductor memory device
    6.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5889304A

    公开(公告)日：1999-03-30

    申请号：US884555

    申请日：1997-06-27

    申请人： Hiroshi Watanabe ,  Kazuhiro Shimizu ,  Yuji Takeuchi ,  Seiichi Aritome

    发明人： Hiroshi Watanabe ,  Kazuhiro Shimizu ,  Yuji Takeuchi ,  Seiichi Aritome

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

    摘要： Disclosed is the memory cell of an EEPROM having a p-type silicon substrate and a floating gate formed on this silicon substrate via a tunnel oxide film. The element region set in the silicon substrate projects from the surface of a trench-type element isolation region. The projecting element region has a curved portion for increasing the density of tunnel electric current, and is rounded to concentrate the tunnel electric current as far as no breakdown occurs in the tunnel oxide film.

    摘要翻译： 公开了具有通过隧道氧化物膜形成在该硅衬底上的p型硅衬底和浮栅的EEPROM的存储单元。 设置在硅衬底中的元件区域从沟槽型元件隔离区域的表面突出。 投影元件区域具有用于增加隧道电流密度的弯曲部分，并且在隧道氧化物膜中不发生击穿的情况下，将隧道电流进行四舍五入以集中。

    Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays
    10.
    发明授权
    Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays 失效
    半导体存储器件具有构成存储单元阵列的多个存储单元晶体管

    公开(公告)号：US6157056A

    公开(公告)日：2000-12-05

    申请号：US8627

    申请日：1998-01-16

    申请人： Yuji Takeuchi ,  Toshiharu Watanabe ,  Seiichi Aritome ,  Hiroshi Watanabe ,  Kazuhiro Shimizu

    发明人： Yuji Takeuchi ,  Toshiharu Watanabe ,  Seiichi Aritome ,  Hiroshi Watanabe ,  Kazuhiro Shimizu

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/708 ,  H01L21/336

    CPC分类号： H01L27/115

    摘要： The semiconductor memory device comprises first and second memory cell rows each constructed by connecting a plurality of memory cell transistors, and third and fourth memory cell rows which are provided to be respectively adjacent to the first and second memory cell rows, such that element separation regions are respectively provided between adjacent memory cell rows. First and second transistors are connected between a drain or a source of the first memory cell row and a drain or a source of the second memory cell row. Gate electrodes of the first and third transistors are connected by a first gate line, and gate electrodes of the second and fourth transistors are connected by a second gate line. The first and second transistors are connected to a data line by a first contact. The third and fourth transistors are connected to a data line by a second contact. A first spacing element is connected between the first and second transistors and a second spacing element is connected between the third and fourth transistors, so that the distance between the first and second contacts is widened. The first contact is provided between the first transistor and the first spacing element. The second contact is provided between the fourth transistor and the second spacing element. The first spacing element is connected through the third gate line to the second spacing element.

    摘要翻译： 半导体存储器件包括通过连接多个存储单元晶体管构成的第一和第二存储单元行，以及分别设置成分别与第一和第二存储单元行相邻的第三和第四存储单元行，使得元件分离区 分别设置在相邻的存储单元行之间。 第一和第二晶体管连接在第一存储单元行的漏极或源极与第二存储单元行的漏极或源极之间。 第一和第三晶体管的栅极通过第一栅极线连接，第二和第四晶体管的栅电极通过第二栅极线连接。 第一和第二晶体管通过第一接触连接到数据线。 第三和第四晶体管通过第二接触连接到数据线。 第一间隔元件连接在第一和第二晶体管之间，第二间隔元件连接在第三和第四晶体管之间，使得第一和第二触点之间的距离变宽。 第一触点设置在第一晶体管和第一间隔元件之间。 第二触点设置在第四晶体管和第二间隔元件之间。 第一间隔元件通过第三栅极线连接到第二间隔元件。