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    Semiconductor memory device
    1.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060171246A1

    公开(公告)日：2006-08-03

    申请号：US11344199

    申请日：2006-02-01

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    IPC分类号： G11C8/00

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

    摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

    Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch
    2.
    发明授权
    Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch 有权

    公开(公告)号：US07006399B2

    公开(公告)日：2006-02-28

    申请号：US11062826

    申请日：2005-02-23

    申请人： Tetsuji Nakakuma ,  Hiroshige Hirano

    发明人： Tetsuji Nakakuma ,  Hiroshige Hirano

    IPC分类号： G11C7/00

    摘要： A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

    Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch
    4.
    发明授权
    Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch 有权
    半导体器件包括差分读出放大器，写入列选择开关和读取列选择开关

    公开(公告)号：US07184344B2

    公开(公告)日：2007-02-27

    申请号：US11062826

    申请日：2005-02-23

    申请人： Tetsuji Nakakuma ,  Hiroshige Hirano

    发明人： Tetsuji Nakakuma ,  Hiroshige Hirano

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/419 ,  G11C2207/002 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897

    摘要： A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

    摘要翻译： 一种半导体器件包括连接到位线的差分读出放大器，以及数据传输电路，包括用于接通/断开数据线与位线之间的连接的列选择开关。 半导体器件包含以下特征之一：列选择开关的导通电阻高于差分读出放大器的晶体管阵列的导通电阻; 单独提供两个列选择开关，一个用于读操作，另一个用于写操作; 提供位线附加电容及其连接控制开关; 并提供数据线分割开关。

    Semiconductor storage device
    5.
    发明申请
    Semiconductor storage device 有权
    半导体存储设备

    公开(公告)号：US20050265090A1

    公开(公告)日：2005-12-01

    申请号：US11121939

    申请日：2005-05-05

    申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

    发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

    IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C29/00 ,  G11C29/12

    CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

    摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

    摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

    Semiconductor memory device with redundant memory cell backup
    7.
    发明授权
    Semiconductor memory device with redundant memory cell backup 失效
    半导体存储器件具有冗余存储单元备份

    公开(公告)号：US5523974A

    公开(公告)日：1996-06-04

    申请号：US344680

    申请日：1994-11-21

    申请人： Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Nobuyuki Moriwaki ,  Toshio Mukunoki ,  Tatsumi Sumi

    发明人： Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Nobuyuki Moriwaki ,  Toshio Mukunoki ,  Tatsumi Sumi

    IPC分类号： G11C11/401 ,  G11C11/22 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C29/789

    摘要： A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.

    摘要翻译： 半导体存储器件包括主存储器单元，冗余存储器单元，冗余地址数据单元，其包括非易失性存储器，其电存储代替主存储单元中的故障存储器单元的冗余存储器单元的地址;控制器 电路15和冗余存储单元选择电路16.冗余存储单元选择电路用于保存从冗余地址数据单元读取的第一地址数据，并将第一地址数据与用于读或写的第二地址数据进行比较 通过控制电路输入的操作，从而选择主存储单元或冗余存储单元。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07280406B2

    公开(公告)日：2007-10-09

    申请号：US11344199

    申请日：2006-02-01

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    IPC分类号： G11C16/06

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

    摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。