公开(公告)号：US08173509B2

公开(公告)日：2012-05-08

申请号：US12714586

申请日：2010-03-01

申请人： Hideki Okumura ,  Takayoshi Nogami ,  Hiroto Misawa

发明人： Hideki Okumura ,  Takayoshi Nogami ,  Hiroto Misawa

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397

摘要： A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.

摘要翻译： 一种半导体器件包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层; 第一导电类型的第三半导体层; 通过栅极绝缘膜形成在栅极沟槽中的多个栅电极，栅极沟槽通过第二半导体层和第三半导体层形成; 多个第二导电类型的杂质区域形成在接触沟底部下方的区域处，所述接触沟槽在第三半导体层的厚度方向上形成在相应的栅极沟槽和触点的纵向截面之间 沟槽分别成椭圆形; 第一电极被形成为分别嵌入接触沟槽并与杂质区域接触; 以及形成在所述半导体衬底的后表面上的第二电极。

公开(公告)号：US07700998B2

公开(公告)日：2010-04-20

申请号：US12164389

申请日：2008-06-30

申请人： Hideki Okumura ,  Takayoshi Nogami ,  Hiroto Misawa

发明人： Hideki Okumura ,  Takayoshi Nogami ,  Hiroto Misawa

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397

摘要： A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.

摘要翻译： 一种半导体器件包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层; 第一导电类型的第三半导体层; 通过栅极绝缘膜形成在栅极沟槽中的多个栅电极，栅极沟槽通过第二半导体层和第三半导体层形成; 多个第二导电类型的杂质区域形成在接触沟底部下方的区域处，所述接触沟槽在第三半导体层的厚度方向上形成在相应的栅极沟槽和触点的纵向截面之间 沟槽分别成椭圆形; 第一电极被形成为分别嵌入接触沟槽并与杂质区域接触; 以及形成在所述半导体衬底的后表面上的第二电极。

公开(公告)号：US08710582B2

公开(公告)日：2014-04-29

申请号：US13420545

申请日：2012-03-14

申请人： Hideki Okumura ,  Hiroto Misawa ,  Takahiro Kawano

发明人： Hideki Okumura ,  Hiroto Misawa ,  Takahiro Kawano

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/2257 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.

公开(公告)号：US20130153995A1

公开(公告)日：2013-06-20

申请号：US13607449

申请日：2012-09-07

申请人： Hiroto MISAWA ,  Hideki Okumura

发明人： Hiroto MISAWA ,  Hideki Okumura

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7397

摘要： A semiconductor device includes a first region with second conductivity type formed over a semiconductor layer with first conductivity type. On this first region, the second region of the first conductivity type is selectively provided. On the same first region, a third region of second conductivity type is also selectively provided and is adjoined to the second region. The first control electrode is provided within a trench located deeper than the first side of the second region compared to the first region. The first control electrode includes a part opposed to the first and second regions separated by a first insulator, and a second part opposed to the semiconductor layer separated by a thicker second insulator. Inside the trench, the second control electrode is provided between the trench bottom and the first control electrode. The second control electrode is opposed to the semiconductor layer through a third insulator.

摘要翻译： 半导体器件包括在具有第一导电类型的半导体层上形成的具有第二导电类型的第一区域。 在该第一区域上，选择性地提供第一导电类型的第二区域。 在相同的第一区域上，也选择性地提供第二导电类型的第三区域并与第二区域邻接。 与第一区域相比，第一控制电极设置在比第二区域的第一侧更深的沟槽内。 第一控制电极包括与由第一绝缘体隔开的第一和第二区域相对的部分，以及与较厚的第二绝缘体隔开的与半导体层相对的第二部分。 在沟槽内，第二控制电极设置在沟槽底部和第一控制电极之间。 第二控制电极通过第三绝缘体与半导体层相对。

公开(公告)号：US07850263B2

公开(公告)日：2010-12-14

申请号：US11755548

申请日：2007-05-30

申请人： Satoshi Shinada ,  Taku Ishizawa ,  Masayoshi Katayama ,  Noboru Asauchi ,  Hideki Okumura

发明人： Satoshi Shinada ,  Taku Ishizawa ,  Masayoshi Katayama ,  Noboru Asauchi ,  Hideki Okumura

IPC分类号： B41J2/195 ,  B41J29/393

CPC分类号： B41J2/17566 ,  B41J2/1753 ,  B41J2/17546 ,  B41J2002/17569 ,  B41J2002/17573 ,  B41J2002/17583

摘要： The invention provides a liquid consumption apparatus including a liquid consumption unit, a counting unit that counts the amount of the liquid consumed by the liquid consumption unit as a liquid consumption amount, a reception unit that receives a detection signal indicating that the amount of the liquid contained in the liquid container is not more than a predetermined amount; a detection-time liquid amount memory unit that memorizes the liquid consumption amount at the time of reception of the detection signal as a detection-time liquid consumption amount, and a judgment unit that judges that the liquid container is empty when the amount of difference between the liquid consumption amount and the detection-time liquid consumption amount is not more than a specified amount.

摘要翻译： 本发明提供了一种液体消耗装置，包括：液体消耗单元;计数单元，其计量由液体消耗单元消耗的液体的量作为液体消耗量;接收单元，其接收指示液体量的检测信号 容纳在液体容器中的量不大于预定量; 检测时间液量存储单元，其将接收到检测信号时的液体消耗量存储为检测时间液体消耗量;以及判断单元，当判断为液体容器为空时， 液体消耗量和检测时间液体消耗量不大于规定量。

公开(公告)号：US20070256300A1

公开(公告)日：2007-11-08

申请号：US11662609

申请日：2005-11-22

申请人： Hideki Okumura ,  Tsuguo Koguchi

发明人： Hideki Okumura ,  Tsuguo Koguchi

IPC分类号： B23P13/00

CPC分类号： F16C9/045 ,  B23C3/30 ,  B23C2215/245 ,  B23C2270/18 ,  B23D45/003 ,  B23D47/12 ,  Y10T29/49288 ,  Y10T409/309576

摘要： A method and a device for machining a cracking groove for a connecting rod, wherein a drive pulley is rotated under the driving action of a rotatingly driving source installed in a body to transmit the rotatingly driving force of the drive pulley to a driven pulley through a drive force transmission belt so as to rotate a groove machining part integrally connected to the driven pulley. In the groove machining part, a spindle integrally connected to the driven pulley is rotatably supported on a support part, and a saw having a plurality of blade parts on the outer peripheral surface thereof is installed on the holding part of the spindle. A first groove of roughly V-shape in cross section is formed in the large end hole of a connecting rod by inserting the metal saw into the large end hole of the connecting rod, and a second groove of roughly V-shape in cross section which is symmetrical with the first groove is formed in the connecting rod at a position opposed to the first groove with respect to the axis of the connecting rod.

摘要翻译： 一种用于加工用于连杆的裂缝槽的方法和装置，其中驱动皮带轮在安装在本体内的旋转驱动源的驱动作用下旋转，以将驱动滑轮的旋转驱动力传递到从动滑轮，通过 驱动力传递带，以使与从动带轮一体连接的槽加工部旋转。 在槽加工部中，与从动带轮一体连接的心轴可旋转地支撑在支撑部上，在其外周面上具有多个叶片部的锯安装在主轴的保持部上。 通过将金属锯插入连杆的大端孔中，在连接杆的大端孔中形成大致V字形的第一槽，并且横截面为大致V形的第二槽 是对称的，第一槽在相对于连杆的轴线与第一槽相对的位置处形成在连杆中。

公开(公告)号：US20050121704A1

公开(公告)日：2005-06-09

申请号：US10983658

申请日：2004-11-09

申请人： Kenichi Tokano ,  Atsuko Yamashita ,  Koichi Takahashi ,  Hideki Okumura ,  Shingo Sato

发明人： Kenichi Tokano ,  Atsuko Yamashita ,  Koichi Takahashi ,  Hideki Okumura ,  Shingo Sato

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66712

摘要： Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a first impurity-diffused region of the first conductivity extending from a lower surface toward an upper surface of the second semiconductor layer, and a second impurity-diffused region of a second conductivity which extends from the lower surface toward the upper surface and is adjacent to the first impurity-diffused region, an insulating layer covering a sidewall of the trench, and a cap layer which is in contact with the semiconductor substrate and covers an opening of the trench to form an enclosed space in the trench, a material of the cap layer being almost the same as that of the semiconductor substrate.

摘要翻译： 提供了一种半导体器件，其包括半导体衬底，该半导体衬底包括第一导电性的第一半导体层和设置在第一半导体层上并且彼此间隔开以在其间形成沟槽的一对第二半导体层，其中第二半导体层包括 从第一半导体层的下表面向上表面延伸的第一导电性的第一杂质扩散区和从下表面向上表面延伸的第二导电性的第二杂质扩散区， 第一杂质扩散区域，覆盖沟槽的侧壁的绝缘层，以及与半导体衬底接触并覆盖沟槽的开口以在沟槽中形成封闭空间的覆盖层，帽的材料 层几乎与半导体衬底的层相同。

公开(公告)号：US20050006699A1

公开(公告)日：2005-01-13

申请号：US10844323

申请日：2004-05-13

申请人： Shingo Sato ,  Atsuko Yamashita ,  Hideki Okumura ,  Kenichi Tokano

发明人： Shingo Sato ,  Atsuko Yamashita ,  Hideki Okumura ,  Kenichi Tokano

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semiconductor base layer between the first semiconductor region and the first semiconductor pillar layer and between the first semiconductor region and the third semiconductor pillar layer, and provided on the second semiconductor base layer between the second semiconductor region and the third semiconductor pillar layer and between the second semiconductor region and the fifth semiconductor pillar layer; and gate electrode provided on the gate insulating film. Each width of the first through fifth semiconductor pillar layers seen in a perpendicular direction to interfaces of p-n junctions formed among the first through fifth semiconductor pillar layers respectively is 10 microns or less.

摘要翻译： 半导体器件包括：第一导电类型的半导体层; 第一导电类型的第一半导体柱层; 第二导电类型的第二半导体柱层; 第一导电类型的第三半导体柱层; 第二导电类型的第四半导体柱层; 设置在半导体层的主表面上的第一导电类型的第五半导体柱层; 设置在第二半导体柱层上的第二导电类型的第一半导体基底层; 设置在第四半导体柱层上的第二导电类型的第二半导体基底层; 选择性地设置在第一半导体基底层的表面上的第一导电类型的第一半导体区域; 选择性地设置在第二半导体基底层的表面上的第一导电类型的第二半导体区域; 栅极绝缘膜，设置在第一半导体基底层之间的第一半导体区域和第一半导体柱层之间以及第一半导体区域和第三半导体柱层之间，并且设置在第二半导体基底层上的第二半导体区域和第三半导体区域之间 半导体柱层和第二半导体区域和第五半导体柱层之间; 以及设置在栅极绝缘膜上的栅电极。 在与第一至第五半导体柱层之间形成的p-n结的界面的垂直方向上分别看到的第一至第五半导体柱层的宽度分别为10微米以下。

公开(公告)号：US06740931B2

公开(公告)日：2004-05-25

申请号：US10417110

申请日：2003-04-17

申请人： Shigeo Kouzuki ,  Hideki Okumura ,  Hitoshi Kobayashi ,  Satoshi Aida ,  Masaru Izumisawa ,  Akihiko Osawa

发明人： Shigeo Kouzuki ,  Hideki Okumura ,  Hitoshi Kobayashi ,  Satoshi Aida ,  Masaru Izumisawa ,  Akihiko Osawa

IPC分类号： H01L2994

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696

摘要： A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.

公开(公告)号：US6010950A

公开(公告)日：2000-01-04

申请号：US026508

申请日：1998-02-19

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L21/02 ,  H01L21/18 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/30

CPC分类号： H01L21/18 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76251 ,  H01L21/76264

摘要： The most distinctive feature of the present invention lies in that a warp and crystal defects can be prevented from occurring and a processing margin for forming an isolation groove can be improved in an intelligent power device including a power element section and an IC control section within one chip. A bonded wafer is obtained by bonding an active-layer substrate and a supporting substrate with an epitaxially grown silicon layer interposed therebetween so as to cover an oxide film selectively formed at the interface of the active-layer substrate. Isolation trenches are then formed in the bonded wafer to such a depth as to reach the oxide film from the element forming surface of the active-layer substrate. Thus, an IC controller is formed within a dielectric isolation region surrounded with the isolation trenches and the oxide film and accordingly the IC controller can effectively be isolated by a dielectric.

摘要翻译： 本发明的最显着的特征在于，可以防止发生翘曲和晶体缺陷，并且可以在包括功率元件部分和IC控制部分的智能功率器件的一个智能功率器件内改善用于形成隔离沟槽的加工余量 芯片。 通过将有源层衬底和支撑衬底与外延生长的硅层接合以便覆盖在有源层衬底的界面处有选择地形成的氧化物膜而获得接合晶片。 然后在接合的晶片中形成隔离沟槽到从活性层衬底的元件形成表面到达氧化物膜的深度。 因此，在由隔离沟槽和氧化物膜包围的电介质隔离区域内形成IC控制器，因此可以通过电介质来有效地隔离IC控制器。