公开(公告)号：US20050121704A1

公开(公告)日：2005-06-09

申请号：US10983658

申请日：2004-11-09

申请人： Kenichi Tokano ,  Atsuko Yamashita ,  Koichi Takahashi ,  Hideki Okumura ,  Shingo Sato

发明人： Kenichi Tokano ,  Atsuko Yamashita ,  Koichi Takahashi ,  Hideki Okumura ,  Shingo Sato

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66712

摘要： Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a first impurity-diffused region of the first conductivity extending from a lower surface toward an upper surface of the second semiconductor layer, and a second impurity-diffused region of a second conductivity which extends from the lower surface toward the upper surface and is adjacent to the first impurity-diffused region, an insulating layer covering a sidewall of the trench, and a cap layer which is in contact with the semiconductor substrate and covers an opening of the trench to form an enclosed space in the trench, a material of the cap layer being almost the same as that of the semiconductor substrate.

摘要翻译： 提供了一种半导体器件，其包括半导体衬底，该半导体衬底包括第一导电性的第一半导体层和设置在第一半导体层上并且彼此间隔开以在其间形成沟槽的一对第二半导体层，其中第二半导体层包括 从第一半导体层的下表面向上表面延伸的第一导电性的第一杂质扩散区和从下表面向上表面延伸的第二导电性的第二杂质扩散区， 第一杂质扩散区域，覆盖沟槽的侧壁的绝缘层，以及与半导体衬底接触并覆盖沟槽的开口以在沟槽中形成封闭空间的覆盖层，帽的材料 层几乎与半导体衬底的层相同。

公开(公告)号：US20050006699A1

公开(公告)日：2005-01-13

申请号：US10844323

申请日：2004-05-13

申请人： Shingo Sato ,  Atsuko Yamashita ,  Hideki Okumura ,  Kenichi Tokano

发明人： Shingo Sato ,  Atsuko Yamashita ,  Hideki Okumura ,  Kenichi Tokano

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semiconductor base layer between the first semiconductor region and the first semiconductor pillar layer and between the first semiconductor region and the third semiconductor pillar layer, and provided on the second semiconductor base layer between the second semiconductor region and the third semiconductor pillar layer and between the second semiconductor region and the fifth semiconductor pillar layer; and gate electrode provided on the gate insulating film. Each width of the first through fifth semiconductor pillar layers seen in a perpendicular direction to interfaces of p-n junctions formed among the first through fifth semiconductor pillar layers respectively is 10 microns or less.

摘要翻译： 半导体器件包括：第一导电类型的半导体层; 第一导电类型的第一半导体柱层; 第二导电类型的第二半导体柱层; 第一导电类型的第三半导体柱层; 第二导电类型的第四半导体柱层; 设置在半导体层的主表面上的第一导电类型的第五半导体柱层; 设置在第二半导体柱层上的第二导电类型的第一半导体基底层; 设置在第四半导体柱层上的第二导电类型的第二半导体基底层; 选择性地设置在第一半导体基底层的表面上的第一导电类型的第一半导体区域; 选择性地设置在第二半导体基底层的表面上的第一导电类型的第二半导体区域; 栅极绝缘膜，设置在第一半导体基底层之间的第一半导体区域和第一半导体柱层之间以及第一半导体区域和第三半导体柱层之间，并且设置在第二半导体基底层上的第二半导体区域和第三半导体区域之间 半导体柱层和第二半导体区域和第五半导体柱层之间; 以及设置在栅极绝缘膜上的栅电极。 在与第一至第五半导体柱层之间形成的p-n结的界面的垂直方向上分别看到的第一至第五半导体柱层的宽度分别为10微米以下。

公开(公告)号：US07391077B2

公开(公告)日：2008-06-24

申请号：US10983658

申请日：2004-11-09

申请人： Kenichi Tokano ,  Atsuko Yamashita ,  Koichi Takahashi ,  Hideki Okumura ,  Shingo Sato

发明人： Kenichi Tokano ,  Atsuko Yamashita ,  Koichi Takahashi ,  Hideki Okumura ,  Shingo Sato

IPC分类号： H01L21/764

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66712

摘要： Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a first impurity-diffused region of the first conductivity extending from a lower surface toward an upper surface of the second semiconductor layer, and a second impurity-diffused region of a second conductivity which extends from the lower surface toward the upper surface and is adjacent to the first impurity-diffused region, an insulating layer covering a sidewall of the trench, and a cap layer which is in contact with the semiconductor substrate and covers an opening of the trench to form an enclosed space in the trench, a material of the cap layer being almost the same as that of the semiconductor substrate.

摘要翻译： 提供了一种半导体器件，其包括半导体衬底，该半导体衬底包括第一导电性的第一半导体层和设置在第一半导体层上并且彼此间隔开以在其间形成沟槽的一对第二半导体层，其中第二半导体层包括 从第一半导体层的下表面向上表面延伸的第一导电性的第一杂质扩散区和从下表面向上表面延伸的第二导电性的第二杂质扩散区， 第一杂质扩散区域，覆盖沟槽的侧壁的绝缘层，以及与半导体衬底接触并覆盖沟槽的开口以在沟槽中形成封闭空间的覆盖层，帽的材料 层几乎与半导体衬底的层相同。

公开(公告)号：US07075149B2

公开(公告)日：2006-07-11

申请号：US10844323

申请日：2004-05-13

申请人： Shingo Sato ,  Atsuko Yamashita ,  Hideki Okumura ,  Kenichi Tokano

发明人： Shingo Sato ,  Atsuko Yamashita ,  Hideki Okumura ,  Kenichi Tokano

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semiconductor base layer between the first semiconductor region and the first semiconductor pillar layer and between the first semiconductor region and the third semiconductor pillar layer, and provided on the second semiconductor base layer between the second semiconductor region and the third semiconductor pillar layer and between the second semiconductor region and the fifth semiconductor pillar layer; and gate electrode provided on the gate insulating film. Each width of the first through fifth semiconductor pillar layers seen in a perpendicular direction to interfaces of p-n junctions formed among the first through fifth semiconductor pillar layers respectively is 10 microns or less.

摘要翻译： 半导体器件包括：第一导电类型的半导体层; 第一导电类型的第一半导体柱层; 第二导电类型的第二半导体柱层; 第一导电类型的第三半导体柱层; 第二导电类型的第四半导体柱层; 设置在半导体层的主表面上的第一导电类型的第五半导体柱层; 设置在第二半导体柱层上的第二导电类型的第一半导体基底层; 设置在第四半导体柱层上的第二导电类型的第二半导体基底层; 选择性地设置在第一半导体基底层的表面上的第一导电类型的第一半导体区域; 选择性地设置在第二半导体基底层的表面上的第一导电类型的第二半导体区域; 栅极绝缘膜，设置在第一半导体基底层之间的第一半导体区域和第一半导体柱层之间以及第一半导体区域和第三半导体柱层之间，并且设置在第二半导体基底层上的第二半导体区域和第三半导体区域之间 半导体柱层和第二半导体区域和第五半导体柱层之间; 以及设置在栅极绝缘膜上的栅电极。 在与第一至第五半导体柱层之间形成的p-n结的界面的垂直方向上分别看到的第一至第五半导体柱层的宽度分别为10微米以下。

公开(公告)号：US07423315B2

公开(公告)日：2008-09-09

申请号：US11265208

申请日：2005-11-03

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

IPC分类号： H01L29/36

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/7811

摘要： The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the third first-conductivity type pillar layer.

摘要翻译： 本申请提供了一种半导体器件，其包括第一导电型半导体衬底，形成在第一导电型半导体衬底上的柱结构部分，并且由平行于第一导电型主要表面的一个方向排列的五个半导体柱层 以及形成在第一导电型半导体基板上并将柱结构部分夹在隔离绝缘部分之间的隔离绝缘部分，其中柱结构部分由第一第一导电型柱层，第二第一导电型支柱层， 导电型柱层和夹着第一第一导电型柱层的第三第一导电型柱层，设置在第一第一导电型柱层和第二第一导电型柱之间的第一第二导电型柱层 层和第二第二导电类型 柱层，设置在第一第一导电型柱层和第三第一导电型柱层之间。

公开(公告)号：US07301202B2

公开(公告)日：2007-11-27

申请号：US11151410

申请日：2005-06-14

申请人： Shigeo Kouzuki ,  Hideki Okumura ,  Wataru Saito ,  Masaru Izumisawa ,  Masahiko Shiomi ,  Hitoshi Kobayashi ,  Kenichi Tokano ,  Satoshi Yanagisawa ,  Hironori Yoshioka ,  Manabu Kimura

发明人： Shigeo Kouzuki ,  Hideki Okumura ,  Wataru Saito ,  Masaru Izumisawa ,  Masahiko Shiomi ,  Hitoshi Kobayashi ,  Kenichi Tokano ,  Satoshi Yanagisawa ,  Hironori Yoshioka ,  Manabu Kimura

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7811

摘要： A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.

摘要翻译： 提供第一导电类型的半导体衬底作为用于多个功率MISFET单元的公共漏极。 在半导体衬底上形成中间半导体层，其杂质浓度低于半导体衬底的杂质浓度。 柱状区域形成在中间半导体层上，并且包括具有比中间半导体层的杂质浓度低的第一导电类型的半导体区域。

公开(公告)号：US20060138536A1

公开(公告)日：2006-06-29

申请号：US11151410

申请日：2005-06-14

申请人： Shigeo Kouzuki ,  Hideki Okumura ,  Wataru Saito ,  Masaru Izumisawa ,  Masahiko Shiomi ,  Hitoshi Kobayashi ,  Kenichi Tokano ,  Satoshi Yanagisawa ,  Hironori Yoshioka ,  Manabu Kimura

发明人： Shigeo Kouzuki ,  Hideki Okumura ,  Wataru Saito ,  Masaru Izumisawa ,  Masahiko Shiomi ,  Hitoshi Kobayashi ,  Kenichi Tokano ,  Satoshi Yanagisawa ,  Hironori Yoshioka ,  Manabu Kimura

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7811

摘要： A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.

摘要翻译： 提供第一导电类型的半导体衬底作为用于多个功率MISFET单元的公共漏极。 在半导体衬底上形成中间半导体层，其杂质浓度低于半导体衬底的杂质浓度。 柱状区域形成在中间半导体层上，并且包括具有比中间半导体层的杂质浓度低的第一导电类型的半导体区域。

公开(公告)号：US20060108600A1

公开(公告)日：2006-05-25

申请号：US11265208

申请日：2005-11-03

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

IPC分类号： H01L29/423

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/7811

摘要： The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the third first-conductivity type pillar layer.

摘要翻译： 本申请提供了一种半导体器件，其包括第一导电型半导体衬底，形成在第一导电型半导体衬底上的柱结构部分，并且由平行于第一导电型主要表面的一个方向排列的五个半导体柱层 以及形成在第一导电型半导体基板上并将柱结构部分夹在隔离绝缘部分之间的隔离绝缘部分，其中柱结构部分由第一第一导电型柱层，第二第一导电型支柱层， 导电型柱层和夹着第一第一导电型柱层的第三第一导电型柱层，设置在第一第一导电型柱层和第二第一导电型柱之间的第一第二导电型柱层 层和第二第二导电类型 柱层，设置在第一第一导电型柱层和第三第一导电型柱层之间。

公开(公告)号：US20060043480A1

公开(公告)日：2006-03-02

申请号：US10991433

申请日：2004-11-19

申请人： Masanobu Tsuchitani ,  Tetsuo Matsuda ,  Hideki Okumura ,  Atsuko Yamashita

发明人： Masanobu Tsuchitani ,  Tetsuo Matsuda ,  Hideki Okumura ,  Atsuko Yamashita

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/42368 ,  H01L29/7811

摘要： A semiconductor device comprises a semiconductor layer which includes a terminate end part and a cell formation part that is surrounded by this end part, and a plurality of guard rings each of which is formed at the end part to surround the cell formation part. These guard rings are made shallower and smaller in width as they get near to the guard ring that resides at the outside position.

摘要翻译： 半导体器件包括半导体层，其包括终端部分和由该端部部分包围的电池形成部分，以及多个保护环，每个保护环形成在端部处以围绕电池形成部分。 这些保护环的宽度越来越小，因为它们靠近位于外部位置的防护环。

公开(公告)号：US07420245B2

公开(公告)日：2008-09-02

申请号：US11194609

申请日：2005-08-02

申请人： Atsuko Yamashita ,  Tetsuo Matsuda ,  Hideki Okumura ,  Masanobu Tsuchitani

发明人： Atsuko Yamashita ,  Tetsuo Matsuda ,  Hideki Okumura ,  Masanobu Tsuchitani

IPC分类号： H01L29/94

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of the first conductivity type is formed adjacent to the second semiconductor pillar layer. A semiconductor base layer of the second conductivity type is formed on the main surface of the second semiconductor pillar layer. An insulated-gate type semiconductor element is formed in the semiconductor base layer. The carrier concentration on the side of a main surface of each of said first through third semiconductor pillar layers is higher than a carrier concentration on the opposite side of said main surface in each of said first through third semiconductor pillar layers.

摘要翻译： 第一导电类型的第一半导体柱层形成在第一导电类型的半导体衬底的主表面上。 形成与第一半导体柱层相邻的第二导电类型的第二半导体柱层。 形成与第二半导体柱层相邻的第一导电类型的第三半导体柱层。 第二导电类型的半导体基底层形成在第二半导体柱层的主表面上。 在半导体基底层中形成绝缘栅型半导体元件。 所述第一〜第三半导体柱层的主表面侧的载流子浓度高于所述第一〜第三半导体柱层的所述主面的相对侧的载流子浓度。