公开(公告)号：US20120216003A1

公开(公告)日：2012-08-23

申请号：US13399185

申请日：2012-02-17

申请人： Hiroto NAKAI ,  Tatsunori Kanai ,  Kenichi Maeda

发明人： Hiroto NAKAI ,  Tatsunori Kanai ,  Kenichi Maeda

IPC分类号： G06F12/00 ,  G06F12/14

CPC分类号： G06F9/524 ,  G06F9/544 ,  G06F12/0246

摘要： According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

摘要翻译： 根据一个实施例，半导体器件包括处理器和存储器件。 存储器件具有非易失性半导体存储器件，并且被配置为用作处理器的主存储器。 当处理器执行多个程序时，处理器管理作为各个程序的工作流程执行程序所需的信息，并创建表，其保持各工作组所需的信息和各条信息的地址之间的关系 在存储器件中，用于各个工作台。 处理器参考相应工作台的相应表访问存储器件。

公开(公告)号：US08892810B2

公开(公告)日：2014-11-18

申请号：US13399185

申请日：2012-02-17

申请人： Hiroto Nakai ,  Tatsunori Kanai ,  Kenichi Maeda

发明人： Hiroto Nakai ,  Tatsunori Kanai ,  Kenichi Maeda

IPC分类号： G06F12/02 ,  G06F9/54

CPC分类号： G06F9/524 ,  G06F9/544 ,  G06F12/0246

摘要： According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

摘要翻译： 根据一个实施例，半导体器件包括处理器和存储器件。 存储器件具有非易失性半导体存储器件，并且被配置为用作处理器的主存储器。 当处理器执行多个程序时，处理器管理作为各个程序的工作流程执行程序所需的信息，并创建表，其保持各工作组所需的信息和各条信息的地址之间的关系 在存储器件中，用于各个工作台。 处理器参考相应工作台的相应表访问存储器件。

公开(公告)号：US20120124290A1

公开(公告)日：2012-05-17

申请号：US13360903

申请日：2012-01-30

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

IPC分类号： G06F12/08

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/7201 ,  G06F2212/7211

摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

摘要翻译： 根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址， 来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及 传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

公开(公告)号：US20100064111A1

公开(公告)日：2010-03-11

申请号：US12555952

申请日：2009-09-09

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda ,  Masaki Miyagawa ,  Hiroshi Nozue ,  Kazuhiro Kawagome

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda ,  Masaki Miyagawa ,  Hiroshi Nozue ,  Kazuhiro Kawagome

IPC分类号： G06F12/00 ,  G06F12/16 ,  G06F12/02

CPC分类号： G06F12/0804 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/7201

摘要： A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

摘要翻译： 根据本发明的示例的设备包括接收来自处理器的写入目的地逻辑地址和写入目标数据的部分，写入目的地逻辑地址指示写入位置以将写入目标数据写入复合存储器，该复合存储器包括第一 存储器和非易失性第二存储器，确定与写入目的地逻辑地址相对应的写目的物理地址的部分，使得对第二存储器的访问次数小于对第一存储器的访问次数， 在存储部中存储将写入目的地逻辑地址与写入目的地物理地址相关联的地址转换数据以及将写入目标数据写入由写入目的地物理地址指示的复合存储器中的位置的部分。

公开(公告)号：US09280466B2

公开(公告)日：2016-03-08

申请号：US12555952

申请日：2009-09-09

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda ,  Masaki Miyagawa ,  Hiroshi Nozue ,  Kazuhiro Kawagome

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda ,  Masaki Miyagawa ,  Hiroshi Nozue ,  Kazuhiro Kawagome

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0804 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/7201

摘要： A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

摘要翻译： 根据本发明的示例的设备包括接收来自处理器的写入目的地逻辑地址和写入目标数据的部分，写入目的地逻辑地址指示写入位置以将写入目标数据写入复合存储器，该复合存储器包括第一 存储器和非易失性第二存储器，确定与写入目的地逻辑地址相对应的写目的物理地址的部分，使得对第二存储器的访问次数小于对第一存储器的访问次数， 在存储部中存储将写入目的地逻辑地址与写入目的地物理地址相关联的地址转换数据以及将写入目标数据写入由写入目的地物理地址指示的复合存储器中的位置的部分。

公开(公告)号：US08458436B2

公开(公告)日：2013-06-04

申请号：US13360903

申请日：2012-01-30

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/7201 ,  G06F2212/7211

摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

摘要翻译： 根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址， 来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及 传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

公开(公告)号：US20090083478A1

公开(公告)日：2009-03-26

申请号：US12236880

申请日：2008-09-24

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/7201 ,  G06F2212/7211

摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

摘要翻译： 根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址， 来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及 传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

公开(公告)号：US08135900B2

公开(公告)日：2012-03-13

申请号：US12236880

申请日：2008-09-24

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/7201 ,  G06F2212/7211

摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

摘要翻译： 根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址， 来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及 传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

公开(公告)号：US09249712B2

公开(公告)日：2016-02-02

申请号：US13158192

申请日：2011-06-10

申请人： Michinori Tani ,  Kenichi Maeda ,  Atsuhiro Miyauchi ,  Seiji Watanabe ,  Soichiro Goto

发明人： Michinori Tani ,  Kenichi Maeda ,  Atsuhiro Miyauchi ,  Seiji Watanabe ,  Soichiro Goto

IPC分类号： F02B27/04 ,  F01N11/00 ,  F02D41/14 ,  F02D41/24

CPC分类号： F01N11/00 ,  F01N2560/025 ,  F02D41/1403 ,  F02D41/1441 ,  F02D41/1482 ,  F02D41/149 ,  F02D41/2454 ,  Y02T10/47

摘要： An air-fuel ratio control system for an internal combustion engine, which, at the resumption of air-fuel ratio feedback control, is capable of setting the initial value of an integral term of the feedback control to a value properly learned in preceding feedback control, thereby enabling improvement of control accuracy. To feedback-control the output value of an O2 sensor to a target value, a target air-fuel ratio is calculated. During the feedback control, when it is determined that a predetermined condition in which it is estimated that exhaust gas air-fuel ratio upstream of the catalyst is excellently reflected on an exhaust gas air-fuel ratio at a location midway or downstream of the catalyst is satisfied, an adaptive law input calculated immediately before interruption of the feedback control is updated and stored as the initial value of an integral term for the following execution of the feedback control.

摘要翻译： 一种用于内燃机的空燃比控制系统，其在恢复空燃比反馈控制时能够将反馈控制的积分项的初始值设定为在先前的反馈控制中正确学习的值 从而能够提高控制精度。 为了将O2传感器的输出值反馈到目标值，计算目标空燃比。 在反馈控制期间，当确定在催化剂上游或下游位置处的排气气体排放气体空气燃料比优异地反映催化剂上游的排气空燃比的预定条件是， 满足于在反馈控制中断之前计算的自适应法则输入被更新并存储为用于随后执行反馈控制的积分项的初始值。

公开(公告)号：US20110320106A1

公开(公告)日：2011-12-29

申请号：US13108014

申请日：2011-05-16

申请人： Michinori TANI ,  Atsuhiro Miyauchi ,  Kenichi Maeda ,  Seiji Watanabe ,  Soichiro Goto

发明人： Michinori TANI ,  Atsuhiro Miyauchi ,  Kenichi Maeda ,  Seiji Watanabe ,  Soichiro Goto

IPC分类号： F02D28/00 ,  F02D1/02

CPC分类号： F02D41/1402 ,  F01N3/101 ,  F02D41/1403 ,  F02D41/1441 ,  F02D41/1454 ,  F02D2041/1409 ,  F02D2200/021 ,  Y02T10/22

摘要： An air-fuel ratio control apparatus for an internal-combustion engine includes an air-fuel-ratio sensor, a control-input calculator, an air-fuel-ratio controller, and a gain calculator. The air-fuel-ratio sensor is disposed in an exhaust channel in the internal-combustion engine and is configured to detect an air-fuel ratio in exhaust gas. The control-input calculator is configured to calculate a control input in accordance with an output value of the air-fuel-ratio sensor. The air-fuel-ratio controller is configured to perform a feedback control using the control input such that the output value of the air-fuel-ratio sensor reaches a target value. The gain calculator is configured to calculate a gain in accordance with the output value when the output value is leaner than the target value. The gain is to be used in calculating the control input.

摘要翻译： 用于内燃机的空燃比控制装置包括空燃比传感器，控制输入计算器，空燃比控制器和增益计算器。 所述空燃比传感器配置在所述内燃机的排气通路中，并且能够检测废气中的空燃比。 控制输入​​计算器被配置为根据空燃比传感器的输出值来计算控制输入。 空燃比控制器被配置为使用控制输入执行反馈控制，使得空燃比传感器的输出值达到目标值。 增益计算器被配置为当输出值比目标值更稀的时候根据输出值来计算增益。 增益用于计算控制输入。