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1.发明申请SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME 失效同步半导体器件及其检测系统及其方法公开(公告)号：US20080204067A1
公开(公告)日：2008-08-28
申请号：US12112782
申请日：2008-04-30
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译： 本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。
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2.发明授权Synchronous semiconductor device, and inspection system and method for the same 失效同步半导体器件及其检测系统及方法相同公开(公告)号：US07378863B2
公开(公告)日：2008-05-27
申请号：US11014789
申请日：2004-12-20
IPC分类号： G01R31/28
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译： 本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。
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3.发明申请SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME 审中-公开同步半导体器件及其检测系统及其方法公开(公告)号：US20100052727A1
公开(公告)日：2010-03-04
申请号：US12614713
申请日：2009-11-09
IPC分类号： G01R31/28
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carry out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will resent a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译： 本发明提供一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地进行老化应力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号重新发出。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。
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4.发明授权Synchronous semiconductor device, and inspection system and method for the same 失效同步半导体器件及其检测系统及方法相同公开(公告)号：US07663392B2
公开(公告)日：2010-02-16
申请号：US12112782
申请日：2008-04-30
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译： 本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。
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5.发明申请Synchronous semiconductor device, and inspection system and method for the same 失效同步半导体器件及其检测系统及方法相同公开(公告)号：US20050111293A1
公开(公告)日：2005-05-26
申请号：US11014789
申请日：2004-12-20
IPC分类号： G01R31/28 , G01R31/317 , G11C8/08 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/34 , G11C8/00
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译： 本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。
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公开(公告)号：US06891393B2
公开(公告)日：2005-05-10
申请号：US10373869
申请日：2003-02-27
IPC分类号： G01R31/28 , G01R31/317 , G11C8/08 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/34
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
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公开(公告)号：US06525975B2
公开(公告)日：2003-02-25
申请号：US09947459
申请日：2001-09-07
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C11/4076
摘要： There is intended to provide a semiconductor integrated circuit device capable of lowering the power consumption during data-write operation, enhancing operation speed, and reducing noises for stable operation. In the semiconductor integrated circuit, an active signal ACT to be inputted to a sense amplifier signal circuit SC1 is latched by a command latch circuit and outputted to a terminal N11. The terminal N11 outputs a control signal EDC1 via a timing adjusting circuit. The control signal EDC1 works to output a sense amplifier activating signal LE via a timing adjusting circuit and output buffer circuit and at the same time, the control signal EDC1 is outputted to a column switch signal circuit CS1. From the Column switch signal circuit CS1, a pulse signal is outputted via input of a control signal ACL, a pulse output circuit, and a terminal N13. In a logical circuit, AND processing is conducted between the pulse signal and an inversion signal of the control signal EDC1. Through a decode circuit, a resultant signal is outputted as switch signal CL, or CLM.
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8.发明授权公开(公告)号：US06741518B2
公开(公告)日：2004-05-25
申请号：US10005345
申请日：2001-12-07
IPC分类号： G11C800
CPC分类号： G11C7/1078 , G11C7/12
摘要： Provided is a semiconductor integrated circuit device capable of, when data is written into a memory cell, fixing adjacent complimentary bit lines to a predetermined voltage, thereby reducing an effect of a write noise for a readout operation of the adjacent cells, making it possible to ensure stable operation. An address signal is inputted to a bit line short signal circuit and a column switch signal circuit, and the corresponding bit line short signal BRS0 or BRS1 and column switch signal CL01 or CL11 are selected. Complimentary bit lines /BL1, /BL2 or bit lines BL1 and BL2 in which a memory cell is not connected according to the bit line short signals BRS0 and BRS1 are selected altogether, these bit lines are fixed to a precharge voltage VPR, and a write noise is shielded. The column switch signal CL01 or CL11 makes conductive the corresponding column switches, and the selected bit line BL1, BL2, /BL1, or /BL2 is connected to a data bus DB or /DB.
摘要翻译： 提供一种半导体集成电路器件，当将数据写入存储单元时，能够将相邻的互补位线固定到预定电压，从而减少对相邻单元的读出操作的写入噪声的影响，使得可以 确保运行稳定。 地址信号输入到位线短信号电路和列切换信号电路，并选择对应的位线短信号BRS0或BRS1以及列切换信号CL01或CL11。 选择根据位线短信号BRS0和BRS1不连接存储单元的空白位线/ BL1，/ BL2或位线BL1和BL2，这些位线被固定为预充电电压VPR，写入 噪音被屏蔽。 列开关信号CL01或CL11使相应的列开关导通，并且所选位线BL1，BL2，/ BL1或/ BL2连接到数据总线DB或/ DB。
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公开(公告)号：US06542421B2
公开(公告)日：2003-04-01
申请号：US09968609
申请日：2001-10-02
申请人： Hiroyuki Sugamoto , Yasushige Ogawa
发明人： Hiroyuki Sugamoto , Yasushige Ogawa
IPC分类号： G11C700
CPC分类号： G11C29/848
摘要： This invention provides a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation. The semiconductor memory device of the present invention includes a plurality of shift switches and a changeover signal generating circuit connected to the shift switches. The changeover signal generating circuit may have a plurality of signal generating blocks including a first signal generating block for generating a first group of changeover signals and a second signal generating block for generating a second group of changeover signals.
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公开(公告)号：US06545940B2
公开(公告)日：2003-04-08
申请号：US09810495
申请日：2001-03-19
IPC分类号： G11C800
CPC分类号： G11C11/4082 , G11C7/1039 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4087
摘要： A semiconductor integrated circuit that acquires an external signal precisely in a high speed operation. The semiconductor integrated circuit includes an internal circuit for acquiring an external signal in response to an address acquisition signal. A first holding circuit is connected to the internal circuit to hold the external signal for a predetermined period in response to a holding signal and provide the held external signal to the internal circuit. A control circuit is connected to the first holding circuit to generate the holding signal using the address acquisition signal.
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