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公开(公告)号：US4747045A
公开(公告)日：1988-05-24
申请号：US749143
申请日：1985-06-26
CPC分类号： G06F9/3861
摘要： An information processing apparatus with an instruction prefetch unit is disclosed, in which a CPU operation can be stopped at a desired address in response to a break signal. The instruction prefetch unit has an instruction prefetch circuit storing an instruction and an indication register storing the break signal. A read operation and a write operation of the indication register are executed together with those of the instruction prefetch circuit. Thus, a break point can be set a desired address by using the indication register, and the break operation can be correctly preformed without the need for complex hardware.
摘要翻译： 公开了一种具有指令预取单元的信息处理装置，其中可以响应于中断信号将CPU操作停止在期望的地址处。 指令预取单元具有存储指令的指令预取电路和存储断点信号的指示寄存器。 与指示预取电路的读取操作和写入操作一起被执行。 因此，通过使用指示寄存器，可以将断点设置为期望的地址，并且可以在不需要复杂的硬件的情况下正确地执行中断操作。
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2.发明授权Semiconductor integrated circuit with external clock signal and reduced data output delay 失效半导体集成电路具有外部时钟信号和减少的数据输出延迟
公开(公告)号：US5454116A
公开(公告)日：1995-09-26
申请号：US19078
申请日：1993-02-18
申请人： Hisao Harigai , Hiroaki Suzuki
发明人： Hisao Harigai , Hiroaki Suzuki
CPC分类号： G06F1/10
摘要： A semiconductor integrated circuit has a clock input buffer, a set of clock drivers, an input buffer, an input latch, an output latch, and a three-state buffer. The clock input buffer produces a first intermediate clock signal in phase with an external clock signal and a second intermediate clock signal out of phase with the external clock signal. With the first intermediate clock signal applied, the set of clock drivers produce non-overlapping two internal clock signals, namely, a first internal clock signal in phase with the external clock signal and a second internal clock signal out of phase with the external clock signal. The input latch is controlled by either the first internal clock signal or the second internal clock signal and latches an output of the input buffer connected to an input/output terminal. The output latch is controlled by the second intermediate clock signal and the latch control signal and latches a signal to be outputted. The three-state buffer outputs an output of the output latch to the input/output terminal. It is possible to reduce, with respect to the external clock signal, the delay time of the data output from the data input/output terminal and also to reduce, for the multi-bit data input/output terminals which operate simultaneously, the output delay time and its variations.
摘要翻译： 半导体集成电路具有时钟输入缓冲器，一组时钟驱动器，输入缓冲器，输入锁存器，输出锁存器和三态缓冲器。 时钟输入缓冲器产生与外部时钟信号同步的第一中间时钟信号和与外部时钟信号异相的第二中间时钟信号。 在施加第一中间时钟信号的情况下，该组时钟驱动器产生非重叠的两个内部时钟信号，即与外部时钟信号同相的第一内部时钟信号和与外部时钟信号异相的第二内部时钟信号 。 输入锁存器由第一内部时钟信号或第二内部时钟信号控制，并锁存连接到输入/输出端子的输入缓冲器的输出。 输出锁存器由第二中间时钟信号和锁存控制信号控制，并锁存要输出的信号。 三态缓冲器将输出锁存器的输出输出到输入/输出端子。 可以相对于外部时钟信号来减少从数据输入/输出端子输出的数据的延迟时间，并且还可以减少对同时工作的多位数据输入/输出端子的输出延迟 时间及其变化。
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公开(公告)号：US5763944A
公开(公告)日：1998-06-09
申请号：US687042
申请日：1996-07-25
申请人： Hisao Harigai
发明人： Hisao Harigai
IPC分类号： H01L23/528 , H01L27/118 , H01L23/50 , H01L23/52
CPC分类号： H01L27/118 , H01L23/528 , H01L2924/0002
摘要： A semiconductor device formed on a semiconductor chip includes a signal processing unit composed of a plurality of signal processing cells arranged side by side in a horizontal direction, and a plurality of input/output cells each connected to a corresponding one of the signal processing cells in a one-to-one relation. The signal processing unit is located near to one corner of the semiconductor chip, and the input/output cells are uniformly distributed and located along two sides defining the above mentioned corner. Each of the signal processing cells is configured to make it possible that a wiring conductor connecting between the signal processing cell and a corresponding one of the input/output cells is taken out either in an upward vertical direction or in a downward vertical direction from the signal processing cell, in accordance with the side of the semiconductor chip along which the corresponding input/output cell is located.
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4.发明授权Memory device, memory system and microcontroller including memory device, and memory control device 有权存储器件，存储器系统和微控制器，包括存储器件和存储器控制器件公开(公告)号：US08539173B2
公开(公告)日：2013-09-17
申请号：US13072262
申请日：2011-03-25
申请人： Hisao Harigai , Toshihide Tsuboi
发明人： Hisao Harigai , Toshihide Tsuboi
CPC分类号： G11C7/1006 , G06F12/0607 , G11C7/1012 , G11C8/10 , Y02D10/13
摘要： A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.
摘要翻译： 存储装置包括：多条字线和位线，其指定要访问的地址; 以及连续地址的多个存储单元，被布置为对应于每个字线。 连续地址的多个存储单元可以通过每个对应于一个存储单元的多个位线并行访问。 在多个字线中，指定与第一字线的地址相邻的地址的第一字线和第二字线具有重叠的地址范围，并且连接到第一字线的第一存储单元和第二存储单元 连接到第二字线的双重方式分配给相同的地址。
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5.发明授权Semiconductor device having a reduced wiring area in and out of data path zone 失效半导体器件具有减少的布线面积进出数据路径区域
公开(公告)号：US5583374A
公开(公告)日：1996-12-10
申请号：US283632
申请日：1994-08-01
申请人： Hisao Harigai
发明人： Hisao Harigai
IPC分类号： H01L21/82 , H01L21/822 , H01L23/528 , H01L27/04 , H01L27/118 , H01L23/50 , H01L23/52
CPC分类号： H01L27/118 , H01L23/528 , H01L2924/0002
摘要： A semiconductor device formed on a semiconductor chip includes a signal processing unit composed of a plurality of signal processing cells arranged side by side in a horizontal direction, and a plurality of input/output cells each connected to a corresponding one of the signal processing cells in a one-to-one relation. The signal processing unit is located near to one corner of the semiconductor chip, and the input/output cells are uniformly distributed and located along two sides defining the above mentioned corner. Each of the signal processing cells is configured to make it possible that a wiring conductor connecting between the signal processing cell and a corresponding one of the input/output cells is taken out either in an upward vertical direction or in a downward vertical direction from the signal processing cell, in accordance with the side of the semiconductor chip along which the corresponding input/output cell is located.
摘要翻译： 形成在半导体芯片上的半导体器件包括由在水平方向上并排配置的多个信号处理单元组成的信号处理单元，以及多个输入/输出单元，每个单元连接到信号处理单元 一对一关系。 信号处理单元位于半导体芯片的一个角附近，并且输入/输出单元均匀地分布并且沿着限定上述拐角的两侧定位。 每个信号处理单元被配置为使得可以在信号处理单元和输入/输出单元中的相应一个单元之间连接的布线导体从信号的上下垂直方向或向下垂直方向取出 处理单元，根据相应的输入/输出单元所位于的半导体芯片的一侧。
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公开(公告)号：US5250895A
公开(公告)日：1993-10-05
申请号：US823785
申请日：1992-01-23
申请人： Hisao Harigai
发明人： Hisao Harigai
CPC分类号： G06F11/24 , G06F11/2273 , G06F11/27
摘要： A method of acceleration testing of reliability of an LSI adopting a microprogram is realized simply. In a test mode, a microaddress is progressively incremented "1" by "1" and data processing within the LSI is executed in accordance with a microcode read out from a control memory based on the microaddress. As for a command decoder and an address generator, external data terminals are clamped to a voltage source or to a ground to permit a specific command to be fetched by the LSI under test. In this way, a majority of internal gates within the LSI are activated while the acceleration test is being conducted on the LSI.
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7.发明授权Data processing system with a pipelined structure for editing trace memory contents and tracing operations during system debugging 失效具有流水线结构的数据处理系统，用于在系统调试期间编辑跟踪存储器内容和跟踪操作
公开(公告)号：US4879646A
公开(公告)日：1989-11-07
申请号：US39900
申请日：1987-04-20
申请人： Junichi Iwasaki , Hisao Harigai
发明人： Junichi Iwasaki , Hisao Harigai
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/34
摘要： A microprocessor having a multi-stage pipeline structure, comprises: a status flip-flop having its output changing when the instruction code of a predetermined instruction is decoded in the microprocessor; a circuit for outputting the output of the status flip-flop in synchronism with the output timing of an address for the bus cycle period of the microprocessor; and a circuit for sequentially storing the information, which appears at the input/output terminals of the microprocessor, as time-series data outside of the microprocessor. The time-series data is edited by discriminating the bus cycle of the microprocessor belongs to the bus cycle following an instruction on or before the predetermined instruction for changing the output of the status flip-flop or the bus cycle following an instruction on or after the predetermined instruction, with reference to the information outputted from the status flip-flop inside of the microprocessor to the outside of the same.
摘要翻译： 一种具有多级流水线结构的微处理器，包括：当在微处理器中解码预定指令的指令代码时，其输出变化的状态触发器; 用于与微处理器的总线周期的地址的输出定时同步地输出状态触发器的输出的电路; 以及用于将出现在微处理器的输入/输出端子处的信息顺序地存储在微处理器外部的时间序列数据的电路。 时间序列数据通过区分属于总线周期的微处理器的总线周期来编辑，该指令在用于改变状态触发器或总线周期的输出的预定指令之前或之前，遵循在指令之后或之后的指令 参考从微处理器内的状态触发器输出到其外部的信息的预定指令。
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