公开(公告)号：US09858181B2

公开(公告)日：2018-01-02

申请号：US14764838

申请日：2013-06-20

申请人： Hitachi, Ltd.

发明人： Yutaka Uematsu ,  Satoshi Muraoka ,  Hiroshi Kakita ,  Akio Idei ,  Yusuke Fukumura ,  Satoru Watanabe ,  Takayuki Ono ,  Taishi Sumikura ,  Yuichi Fukuda ,  Takashi Miyagawa ,  Michinori Naito ,  Hideki Osaka ,  Masabumi Shibata ,  Hitoshi Ueno ,  Kazunori Nakajima ,  Yoshihiro Kondo

IPC分类号： G06F13/00 ,  G06F12/02 ,  G11C5/04 ,  G11C11/00 ,  G06F12/06 ,  G11C7/10 ,  G11C16/04

CPC分类号： G06F12/0246 ,  G06F12/0638 ,  G06F2212/2532 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/005 ,  G11C16/0491

摘要： A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

公开(公告)号：US09658783B2

公开(公告)日：2017-05-23

申请号：US14759504

申请日：2013-03-27

申请人： Hitachi, Ltd.

发明人： Satoshi Muraoka ,  Yutaka Uematsu ,  Hideki Osaka ,  Yuusuke Fukumura ,  Satoru Watanabe ,  Masabumi Shibata ,  Hiroshi Kakita ,  Yuichi Fukuda ,  Takashi Miyagawa ,  Michinori Naito ,  Hitoshi Ueno ,  Akio Idei ,  Takayuki Ono ,  Taishi Sumikura

IPC分类号： G11C5/04 ,  G11C7/10 ,  G06F3/06 ,  G06F13/16

CPC分类号： G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1694 ,  G11C5/04 ,  G11C7/10

摘要： In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

公开(公告)号：US09569144B2

公开(公告)日：2017-02-14

申请号：US14763019

申请日：2013-03-27

申请人： Hitachi, Ltd.

发明人： Yutaka Uematsu ,  Satoshi Muraoka ,  Hideki Osaka ,  Masabumi Shibata ,  Yuusuke Fukumura ,  Satoru Watanabe ,  Hiroshi Kakita ,  Akio Idei ,  Hitoshi Ueno ,  Takayuki Ono ,  Takashi Miyagawa ,  Michinori Naito ,  Taishi Sumikura ,  Yuichi Fukuda

IPC分类号： G11C14/00 ,  G06F3/06 ,  G11C5/04 ,  G06F13/16 ,  G11C7/10

CPC分类号： G06F3/068 ,  G06F3/0611 ,  G06F3/0629 ,  G06F13/1694 ,  G11C5/04 ,  G11C7/10

摘要： When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

摘要翻译： 作为速度较低但容量大于DRAM的高速存储器和闪速存储器的DRAM将被安装在DIMM上时，最大限度地提高CPU存储器总线吞吐量的重要性是安装组件的布置。 本公开提供了一种存储器模块（DIMM），其包括布置在更靠近插座端子的模块表面上的存储器控​​制器和用作布置在背面上的高速存储器的DRAM。 作为大容量存储器的非易失性存储器被布置在距离插座端子更远的一侧。