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公开(公告)号：US20200033122A1
公开(公告)日：2020-01-30
申请号：US16337694
申请日：2017-08-04
Applicant: Hitachi High-Technologies Corporation
Inventor： Yasutaka TOYODA , Hiroyuki SHINDO
IPC: G01B15/04
Abstract: The present invention is intended to provide a pattern evaluation apparatus and a computer program aimed at achieving defect inspection with high efficiency and high precision while allowing manufacturing variations that are dissimilar depending on the sites of a circuit. In order to achieve the above object, proposed are a computer program and an inspection system having a means of performing statistical processing of measurement data of a plurality of inspection target patterns having similar or same design pattern shape used for manufacturing the inspection target patterns, and performing adjustment of a defect determination threshold in accordance with a distribution state of measurement data.
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公开(公告)号：US20130117723A1
公开(公告)日：2013-05-09
申请号：US13712611
申请日：2012-12-12
Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
Inventor： Yasutaka TOYODA , Ryoichi MATSUOKA , Akiyuki SUGIYAMA
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06K9/00 , G06K2209/19 , G06T7/0004
Abstract: A pattern shape evaluation method and semiconductor inspection system having a unit for extracting contour data of a pattern from an image obtained by photographing a semiconductor pattern, a unit for generating pattern direction data from design data of the semiconductor pattern, and a unit for detecting a defect of a pattern, through comparison between pattern direction data obtained from the contour data and pattern direction data generated from the design data corresponding to a pattern position of the contour data.
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公开(公告)号：US20210383524A1
公开(公告)日：2021-12-09
申请号：US17410344
申请日：2021-08-24
Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
Inventor： Shuyang DOU , Shinichi SHINODA , Yasutaka TOYODA , Hiroyuki SHINDO
Abstract: A pattern inspection system inspects an image of an inspection target pattern of an electronic device using an identifier constituted by machine learning, based on the image of the inspection target pattern of the electronic device and data used to manufacture the inspection target pattern. The system includes a storage unit which stores a plurality of pattern images of the electronic device and pattern data used to manufacture a pattern of the electronic device, and an image selection unit which selects a learning pattern image used in the machine learning from the plurality of pattern images, based on the pattern data and the pattern image stored in the storage unit.
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公开(公告)号：US20200074611A1
公开(公告)日：2020-03-05
申请号：US16557175
申请日：2019-08-30
Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
Inventor： Shuyang DOU , Shinichi SHINODA , Yasutaka TOYODA , Hiroyuki SHINDO
Abstract: A pattern inspection system inspects an image of an inspection target pattern of an electronic device using an identifier constituted by machine learning, based on the image of the inspection target pattern of the electronic device and data used to manufacture the inspection target pattern. The system includes a storage unit which stores a plurality of pattern images of the electronic device and pattern data used to manufacture a pattern of the electronic device, and an image selection unit which selects a learning pattern image used in the machine learning from the plurality of pattern images, based on the pattern data and the pattern image stored in the storage unit.
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公开(公告)号：US20170336717A1
公开(公告)日：2017-11-23
申请号：US15536255
申请日：2015-12-18
Applicant: Hitachi High-Technologies Corporation
Inventor： Shinichi SHINODA , Yasutaka TOYODA , Hiroyuki USHIBA , Hitoshi SUGAHARA
IPC: G03F7/20
Abstract: The purpose of the present invention is to provide an exposure condition evaluation device that appropriately evaluates a wafer exposure condition or calculates an appropriate exposure condition, on the basis of information obtained from an FEM wafer, without relying on the formation state of the FEM wafer. In order to achieve the foregoing, the present invention proposes an exposure condition evaluation device which evaluates an exposure condition of a reduction projection exposure device, on the basis of the information of patterns exposed on a sample by the reduction projection exposure device, and which uses a second feature amount of a plurality of patterns formed by making exposure conditions uniform to correct a first feature amount of a plurality of patterns formed by a plurality of different exposure condition settings.
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Patent Agency Ranking
公开(公告)号：US20180247400A1
公开(公告)日：2018-08-30
申请号：US15964559
申请日：2018-04-27
Applicant: Hitachi High-Technologies Corporation
Inventor： Yasutaka TOYODA , Norio HASEGAWA , Takeshi KATO , Hitoshi SUGAHARA , Yutaka HOJO , Daisuke HIBINO , Hiroyuki SHINDO
IPC: G06T7/00 , H01J37/22 , G01N23/2251 , H01J37/28 , H01L21/66 , G01N23/225
CPC classification number: G06T7/001 , G01N23/225 , G01N23/2251 , G01N2223/6113 , G06T2207/10061 , G06T2207/30148 , H01J37/222 , H01J37/28 , H01J2237/221 , H01J2237/2817 , H01L22/12
Abstract: A pattern-measuring apparatus and a semiconductor-measuring system are provided which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In particular, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.
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公开(公告)号：US20160356598A1
公开(公告)日：2016-12-08
申请号：US15117964
申请日：2015-01-07
Applicant: Hitachi High-Technologies Corporation
Inventor： Yasutaka TOYODA , Hiroyuki SINDO
IPC: G01B15/00 , G01N23/225
CPC classification number: G01B15/00 , G01B2210/56 , G01N23/203 , G01N23/2251 , G01N2223/6116 , H01L22/12
Abstract: In order to provide a pattern-measuring device and a computer program that quantitatively evaluate the effects brought about by the presence of pattern deformations in a circuit, this invention proposes a pattern-measuring device that measures first distances between first edges in pattern data being measured and second edges that correspond to said first edges in a benchmark pattern that corresponds to the pattern being measured. Said pattern-measuring device computes a score for the first edges or the pattern being measured on the basis of the first distances and second distances between the first edges and/or the second edges and third edges that are adjacent to but different from the first and second edges.
Abstract translation: 为了提供一种模式测量装置和计算机程序，其定量地评估由于在电路中存在图案变形而产生的影响，本发明提出了一种图形测量装置，其测量被测量的图案数据中的第一边缘之间的第一距离 以及对应于与被测量的图案相对应的基准图案中的所述第一边缘的第二边缘。 所述图案测量装置基于第一边缘和/或第二边缘和/或第二边缘和第三边缘之间的第一距离和第二距离来计算针对所测量的第一边缘或图案的分数，第二边缘和第三边缘与第一边缘或第二边缘相邻但不同于第一边缘 第二边。
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公开(公告)号：US20130325397A1
公开(公告)日：2013-12-05
申请号：US13789619
申请日：2013-03-07
Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
Inventor： Tsuyoshi Minakawa , Yasutaka TOYODA
IPC: G01B21/20
CPC classification number: G01B21/20 , G01B2210/56 , G01N21/95607
Abstract: A dimension measuring apparatus for measuring a dimension between a first contour data which is an evaluation reference of a pattern to be evaluated and a second contour data which is the pattern to be evaluated generates first correspondence information between a point on the first contour data and a point on the second contour data, determines consistency of a correspondence included in the first correspondence information, corrects an inconsistent correspondence, and generates second correspondence information, when associating a point on the first contour data and a point on the second contour data with each other.
Abstract translation: 一种尺寸测量装置，用于测量作为待评估图案的评估基准的第一轮廓数据和作为待评估图案的第二轮廓数据之间的尺寸，生成第一轮廓数据上的点与第一轮廓数据之间的第一对应信息 指定第二轮廓数据时，确定包含在第一对应信息中的一致性的一致性，校正不一致的对应关系，并且当将第一轮廓数据上的点与第二轮廓数据上的点相互关联时产生第二对应信息 。
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公开(公告)号：US20130315468A1
公开(公告)日：2013-11-28
申请号：US13959384
申请日：2013-08-05
Applicant: Hitachi High-Technologies Corporation
Inventor： Yasutaka TOYODA , Hideo SAKAI , Ryoichi MATSUOKA
IPC: G06T7/00
CPC classification number: G06K9/00 , G01R31/31813 , G06K9/6255 , G06T7/001 , G06T2207/30141
Abstract: Although there has been a method for evaluating pattern shapes of electronic devices by using, as a reference pattern, design data or a non-defective pattern, the conventional method has a problem that the pattern shape cannot be evaluated with high accuracy because of the difficulty in defining an exact shape suitable for the manufacturing conditions of the electronic devices. The present invention provides a shape evaluation method for circuit patterns of electronic devices, the method including a means for generating contour distribution data of at least two circuit patterns from contour data sets on the circuit patterns; a means for generating a reference pattern used for the pattern shape evaluation, from the contour distribution data; and a means for evaluating the pattern shape by comparing each evaluation target pattern with the reference pattern.
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公开(公告)号：US20190228522A1
公开(公告)日：2019-07-25
申请号：US16252061
申请日：2019-01-18
Applicant: Hitachi High-Technologies Corporation
Inventor： Shinichi SHINODA , Masayoshi ISHIKAWA , Yasutaka TOYODA , Yuichi ABE , Hiroyuki SHINDO
Abstract: The image evaluation device includes a design data image generation unit that images design data; a machine learning unit that creates a model for generating a design data image from an inspection target image, using the design data image as a teacher and using the inspection target image corresponding to the design data image; a design data prediction image generation unit that predicts the design data image from the inspection target image, using the model created by the machine learning unit; a design data image generation unit that images the design data corresponding to the inspection target image; and a comparison unit that compares a design data prediction image generated by the design data prediction image generation unit and the design data image. As a result, it is possible to detect a systematic defect without using a defect image and generating misinformation frequently.
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