公开(公告)号：US6166406A

公开(公告)日：2000-12-26

申请号：US153341

申请日：1998-09-15

申请人： Hitoshi Yamada ,  Sanpei Miyamoto

发明人： Hitoshi Yamada ,  Sanpei Miyamoto

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/4094 ,  G11C16/06 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C7/12 ,  G11C11/4094 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/908

摘要： In the present invention, a precharge circuit includes a precharge supply for setting equal potentials at pairs of spaced signal lines extending in parallel with respect to each other, a pair of switching elements for connecting and disconnecting respective signal lines to the supply, and a short circuit switching element for connecting and disconnecting short circuiting of the signal lines. The short circuit switching element consists of a transistor comprising a source and drain constituted by a pair of impurity regions formed underneath the pair of signal lines so as to correspond to the pair of signal lines and a gate. The gate of the transistor is formed in such a manner that gate length coincides with the widthwise direction of the pair of signal lines.

摘要翻译： 在本发明中，预充电电路包括用于在彼此平行延伸的成对的间隔信号线设置相等电位的预充电电源，用于连接和断开与供电相关的信号线的一对开关元件，以及短路 电路开关元件，用于连接和断开信号线的短路。 短路开关元件由包括源极和漏极的晶体管组成，源极和漏极由形成在该对信号线下方的一对杂质区域构成，以便对应于该对信号线和栅极。 晶体管的栅极以栅极长度与一对信号线的宽度方向一致的方式形成。

公开(公告)号：US5040151A

公开(公告)日：1991-08-13

申请号：US644988

申请日：1991-01-23

申请人： Masahumi Miyawaki ,  Sanpei Miyamoto

发明人： Masahumi Miyawaki ,  Sanpei Miyamoto

IPC分类号： G11C11/401 ,  G11C5/14 ,  G11C7/10 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10

CPC分类号： G11C7/1057 ,  G11C5/14 ,  G11C7/1051 ,  G11C2207/108

摘要： A memory circuit has a Vcc post that is connected to a Vcc pad and is optionally connectable to a mode pad. The memory circuit also has N data output buffers, M of which operate regardless of whether the Vcc post is connected to the mode pad or not. These M data output buffers are all powered from the Vcc pad. The remaining N-M data output buffers operate only when the Vcc post is connected to the mode pad; at least one of these N-M data output buffers is powered from the mode pad, thereby reducing the potential drop at the Vcc pad.

公开(公告)号：US5192878A

公开(公告)日：1993-03-09

申请号：US799866

申请日：1991-11-27

申请人： Sanpei Miyamoto ,  Hidetoshi Uehara

发明人： Sanpei Miyamoto ,  Hidetoshi Uehara

IPC分类号： H03K3/356

CPC分类号： H03K3/356165 ,  H03K3/356113 ,  H03K3/356147

摘要： A differential amplifier compares a potential difference between a first input (A.sub.in) and a second input (V.sub.r) and provides complementary output signals (A, A). The differential amplifier comprises a flip-flop (20) having nodes (N1, N2) and nodes (N3, N4) and a fixing means composed of N-channel FETs (33, 34) having drains connected to the nodes (N3, N4) of the flip-flop circuit (20) and sources connected to a second potential (V.sub.SS) and inverters (31, 32) having inputs to which output signals (A, A) are applied and outputs connected to gates of the N-channel FETs (33, 34). The fixing means detects a potential drop of the output signals (A, A) and fixing the nodes (N3, N4) connected to the nodes (N1, N2) to the second potential (V.sub.SS).

摘要翻译： 差分放大器比较第一输入（Ain）和第二输入（Vr）之间的电位差，并提供互补输出信号（A，＆amp;上升和下降）。 差分放大器包括具有节点（N1，N2）和节点（N3，N4）的触发器（20）和由具有连接到节点（N3，N4）的漏极的N沟道FET（33,34）组成的固定装置 ）和连接到第二电位（VSS）的源和具有输入的反相器（31,32）的反相器（31,32），输入端连接到输出信号（A，＆amp; 沟道FET（33,34）。 固定装置检测输出信号（A，＆amp; upbar＆A）的电位降，并将连接到节点（N1，N2）的节点（N3，N4）固定到第二电位（VSS）。

公开(公告)号：US5177586A

公开(公告)日：1993-01-05

申请号：US818803

申请日：1992-01-09

申请人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Sanpei Miyamoto ,  Hidenori Uehara

发明人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Sanpei Miyamoto ,  Hidenori Uehara

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108

CPC分类号： H01L27/0921 ,  G11C11/4074 ,  G11C11/4091 ,  G11C7/065 ,  H01L27/088

摘要： A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

公开(公告)号：US5087957A

公开(公告)日：1992-02-11

申请号：US672359

申请日：1991-03-20

申请人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Sanpei Miyamoto ,  Hidenori Uehara

发明人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Sanpei Miyamoto ,  Hidenori Uehara

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108

CPC分类号： H01L27/0921 ,  G11C11/4074 ,  G11C11/4091 ,  G11C7/065 ,  H01L27/088

摘要： A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

摘要翻译： CMOS存储器件具有存储单元阵列，形成在第一导电类型的衬底上，用于存储数据。 通过连接到存储单元阵列的位线对来输入和输出数据。 嵌入在第二导电类型的阱中的第一导电类型的感测放大器放大位线对上的电位差。 感测放大器连接到读出放大器驱动信号线并由其驱动。 读出放大器驱动信号线还偏置包含读出放大器的阱，从而防止闩锁。