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    Semiconductor memory device with resistive power supply connection
    3.
    发明授权
    Semiconductor memory device with resistive power supply connection 失效
    具有电阻电源连接的半导体存储器件

    公开(公告)号：US5517444A

    公开(公告)日：1996-05-14

    申请号：US397730

    申请日：1995-03-02

    申请人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Yoshio Ohtsuki

    发明人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Yoshio Ohtsuki

    IPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C7/00

    CPC分类号： G11C11/4074 ,  G11C5/147

    摘要： In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal. Still alternatively, the transistors which are turned on by a control signal to connect the sense amplifiers to a power supply main line have a different mutual conductance depending on the resistance of the power supply line.

    摘要翻译： 在具有多个存储单元阵列的半导体存储器件中，其中存储单元连接的一对位线之间的电位差通过响应于公共节点上的读出锁存信号而工作的读出放大器放大，并且存储器单元 通过电源线连接到电源，消除或减少由于电源线的电阻引起的不利影响。 这是通过将布置在每个存储单元阵列内的电源辅助线和沿着存储单元阵列布置的电源主线通过电阻大于电源主线的电阻的电阻元件而耦合来实现的 提供给位于最远的存储单元阵列。 或者，每个存储单元阵列中的公共节点经由电阻元件和通过控制信号导通和截止的读出放大器驱动晶体管连接到所述电源主线。 或者，通过控制信号导通以将读出放大器连接到电源主线的晶体管根据电源线的电阻具有不同的互导。

    Semiconductor memory device with noise reduction system
    4.
    发明授权
    Semiconductor memory device with noise reduction system 失效
    具有降噪系统的半导体存储器件

    公开(公告)号：US5280453A

    公开(公告)日：1994-01-18

    申请号：US705341

    申请日：1991-05-24

    申请人： Masahumi Miyawaki ,  Tamihiro Ishimura

    发明人： Masahumi Miyawaki ,  Tamihiro Ishimura

    IPC分类号： G11C11/4091 ,  G11C7/02

    CPC分类号： G11C11/4091

    摘要： An integrated circuit semiconductor memory device includes a memory array having memory cells. A sensing circuit is coupled to the memory cells through one of first and second bit lines. A first conductive line is for applying a first voltage potential to the sensing circuit, and a second conductive line is for applying a second voltage potential to the sensing circuit. A first field effect transistor is provided having first, second electrodes connected to the first conductive line, and a gate electrode connected to the second conductive line. The sensing circuit has a second field effect transistor and a third field effect transistor of an opposite channel type to the second field effect transistor. The first, second and gate electrodes of the first field effect transistor are formed substantially simultaneously with the first, second and gate electrodes of one of the second and third field effect transistors during manufacture of the integrated circuit semiconductor memory device. Also, the first conductive line is formed substantially simultaneously with the second conductive line during manufacture of the integrated circuit semiconductor memory device.

    摘要翻译： 集成电路半导体存储器件包括具有存储单元的存储器阵列。 感测电路通过第一和第二位线之一耦合到存储器单元。 第一导线用于向感测电路施加第一电压电位，第二导线用于向感测电路施加第二电压电位。 提供第一场效应晶体管，其具有连接到第一导线的第一，第二电极和连接到第二导线的栅电极。 感测电路具有与第二场效应晶体管相反通道类型的第二场效应晶体管和第三场效应晶体管。 在集成电路半导体存储器件的制造期间，第一场效应晶体管的第一，第二和第二栅极电极基本上与第二和第三场效应晶体管之一的第一，第二和第二栅极电极形成同时。 此外，在集成电路半导体存储器件的制造期间，第一导线基本上与第二导线形成同时形成。

    Dual current data bus clamp circuit of semiconductor memory device
    5.
    发明授权
    Dual current data bus clamp circuit of semiconductor memory device 失效
    半导体存储器件的双电流数据总线钳位电路

    公开(公告)号：US5091886A

    公开(公告)日：1992-02-25

    申请号：US706206

    申请日：1991-05-28

    申请人： Masahumi Miyawaki ,  Tamihiro Ishimura ,  Yoshio Ohtsuki

    发明人： Masahumi Miyawaki ,  Tamihiro Ishimura ,  Yoshio Ohtsuki

    IPC分类号： G11C11/409 ,  G11C7/10

    CPC分类号： G11C7/1048

    摘要： A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit for discharging electric charge on the complementary data buses during an active period of the row address strobe signal, and a second discharge circuit for discharging electric charge on the complementary data buses with a discharge ability larger than the first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.

    Semiconductor memory device being coupled by auxiliary power lines to a main power line
    6.
    发明授权
    Semiconductor memory device being coupled by auxiliary power lines to a main power line 失效
    半导体存储器件通过辅助电源线耦合到主电源线

    公开(公告)号：US5321658A

    公开(公告)日：1994-06-14

    申请号：US702496

    申请日：1991-05-20

    申请人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Yoshio Ohtsuki

    发明人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Yoshio Ohtsuki

    IPC分类号： G11C5/14 ,  G11C11/4074

    CPC分类号： G11C11/4074 ,  G11C5/147

    摘要： In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal. Still alternatively, the transistors which are turned on by a control signal to connect the sense amplifiers to a power supply main line have a different mutual conductance depending on the resistance of the power supply line.

    摘要翻译： 在具有多个存储单元阵列的半导体存储器件中，其中存储单元连接的一对位线之间的电位差通过响应于公共节点上的读出锁存信号而工作的读出放大器放大，并且存储器单元 通过电源线连接到电源，消除或减少由于电源线的电阻引起的不利影响。 这是通过将布置在每个存储单元阵列内的电源辅助线和沿着存储单元阵列布置的电源主线通过电阻大于电源主线的电阻的电阻元件而耦合来实现的 提供给位于最远的存储单元阵列。 或者，每个存储单元阵列中的公共节点经由电阻元件和通过控制信号导通和截止的读出放大器驱动晶体管连接到所述电源主线。 或者，通过控制信号导通以将读出放大器连接到电源主线的晶体管根据电源线的电阻具有不同的互导。

    Data bus clamp circuit for a semiconductor memory device
    7.
    发明授权
    Data bus clamp circuit for a semiconductor memory device 失效
    用于半导体存储器件的数据总线钳位电路

    公开(公告)号：US5260904A

    公开(公告)日：1993-11-09

    申请号：US797954

    申请日：1991-11-26

    申请人： Masahumi Miyawaki ,  Tamihiro Ishimura ,  Yoshio Ohtsuki

    发明人： Masahumi Miyawaki ,  Tamihiro Ishimura ,  Yoshio Ohtsuki

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1048

    摘要： A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit for discharging electric charge on the complementary data buses during an active period of the row address strobe signal, and a second discharge circuit for discharging electric charge on the complementary data buses with a discharge ability larger than the first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.

    摘要翻译： 用于半导体存储器件的数据总线钳位电路包括用于存储数据的存储单元阵列，行地址解码器，用于解码通过行地址选通信号取入的行地址信号，以选择存储单元的行方向上的存储单元 阵列，列地址解码器，用于基于列地址解码器使能信号来选择存储单元阵列的列方向上的存储单元来解码列地址信号，用于发送从存储单元阵列读出的数据的补充数据总线，数据总线 用于提升互补数据总线的上拉电路，以及差分放大型读出电路，用于在差分基础上放大互补数据总线上的数据以输出读出数据。 数据总线钳位电路包括：第一放电电路，用于在行地址选通信号的有效期间内对互补数据总线上的电荷进行放电;以及第二放电电路，用于放电补充数据总线上的电荷大于 在从行地址选通信号的有效周期开始到列地址译码器使能信号变为有效的时间段期间，第一放电电路。

    Drive circuit with a ring oscillator for a semiconductor device
    8.
    发明授权
    Drive circuit with a ring oscillator for a semiconductor device 失效
    具有用于半导体器件的环形振荡器的驱动电路

    公开(公告)号：US4843258A

    公开(公告)日：1989-06-27

    申请号：US226087

    申请日：1988-07-29

    申请人： Masahumi Miyawaki ,  Sampei Miyamoto ,  Tamihiro Ishimura

    发明人： Masahumi Miyawaki ,  Sampei Miyamoto ,  Tamihiro Ishimura

    IPC分类号： G05F3/24 ,  G11C11/407 ,  G11C11/413 ,  H02M3/07 ,  H03K3/03 ,  H03K3/354

    CPC分类号： G05F3/24 ,  H03K3/0315 ,  H03K3/354

    摘要： A drive circuit for driving a semiconductor device includes a reference voltage level generator for outputting a reference voltage level which is associated with an input voltage level from an external power source. Supplied with the reference level, a ring oscillator oscillates a frequency signal having a predetermined frequency. A drive voltage level generator responds to the reference level and the frequency signal for producing a drive voltage level which is constantly substantially equal to the reference level in synchronism with the frequency signal. The drive voltage level generator feeds power from the external power source to the semiconductor device at the drive level, thereby driving the semiconductor load circuit.

    摘要翻译： 用于驱动半导体器件的驱动电路包括用于输出与来自外部电源的输入电压电平相关联的参考电压电平的参考电压电平发生器。 提供参考电平，环形振荡器振荡具有预定频率的频率信号。 驱动电压电平发生器响应参考电平和频率信号，以产生与频率信号同步地恒定地基本上等于参考电平的驱动电压电平。 驱动电压电平发生器将来自外部电源的功率从驱动电平提供给半导体器件，由此驱动半导体负载电路。

    Power supply circuit
    10.
    发明授权
    Power supply circuit 失效
    电源电路

    公开(公告)号：US6166588A

    公开(公告)日：2000-12-26

    申请号：US213420

    申请日：1998-12-17

    申请人： Masahumi Miyawaki

    发明人： Masahumi Miyawaki

    IPC分类号： G11C16/06 ,  G05F3/24 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G05F3/02

    CPC分类号： G05F3/242

    摘要： A power supply circuit comprising a reference voltage generating circuit and an internal voltage generating circuit, whereby a stable internal voltage can be supplied. The reference voltage generating circuit comprises a resistor, of which one end is coupled to a power supply terminal, and a first NMOSFET, of which the drain electrode is coupled to the other end of the resistor, the source electrode is coupled to an earth terminal, and the gate electrode is coupled to the drain electrode. The internal voltage generating circuit comprises a second NMOSFET, of which the gate electrode is coupled to the drain electrode of the first NMOSFET and the source electrode is coupled to the earth terminal, and a constant voltage generating circuit, coupled between the drain electrode of the second NMOSFET and the power supply terminal, which outputs a constant voltage. The gate length of the first NMOSFET is formed longer than the gate length of the second NMOSFET.

    摘要翻译： 一种电源电路，包括基准电压发生电路和内部电压产生电路，由此可以提供稳定的内部电压。 参考电压产生电路包括一个电阻器，其一端耦合到电源端子，第一NMOSFET，其漏极连接到电阻器的另一端，源极耦合到接地端子 并且栅电极耦合到漏电极。 内部电压产生电路包括第二NMOSFET，栅电极连接到第一NMOSFET的漏电极，源电极耦合到接地端子，以及恒压产生电路，其连接在第一NMOSFET的漏电极 第二NMOSFET和输出恒定电压的电源端子。 第一NMOSFET的栅极长度形成为比第二NMOSFET的栅极长度长。