公开(公告)号：US07295055B2

公开(公告)日：2007-11-13

申请号：US11216142

申请日：2005-09-01

申请人： Hidekazu Noguchi ,  Hidenori Uehara

发明人： Hidekazu Noguchi ,  Hidenori Uehara

IPC分类号： G06F1/04

CPC分类号： H04N5/3577

摘要： A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at “L” during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal. In the meantime, the signal from the second NAND gate is also inverted by an inverter, and is supplied as an internal clock to the data input portion, data processing portion, and data output portion.

摘要翻译： 半导体集成电路包括具有第一积分部和第二积分部的积分电路。 半导体集成电路还包括数据输入部分，数据处理部分和数据输出部分。 时钟信号由输入缓冲器反相，并与掩模信号一起施加到NAND门。 当来自NAND门的信号上升时，由于积分电路，第二积分部分的信号落在延迟时间之后。 来自NAND门的信号与来自第二积分部分的信号一起施加到第二NAND门，并且来自第二NAND门的信号在从时钟信号上升的时间段期间固定为“L” 在积分电路的延迟时间的持续时间内。 来自第二NAND门的信号被第三积分部分延迟，并且第三积分部分的延迟时间由与门相加以产生掩模信号。 同时，来自第二NAND门的信号也被反相器反相，并作为内部时钟提供给数据输入部分，数据处理部分和数据输出部分。

公开(公告)号：US20060119716A1

公开(公告)日：2006-06-08

申请号：US11216142

申请日：2005-09-01

申请人： Hidekazu Noguchi ,  Hidenori Uehara

发明人： Hidekazu Noguchi ,  Hidenori Uehara

IPC分类号： H04N5/335 ,  H04N3/14

CPC分类号： H04N5/3577

摘要： A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at “L” during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal. In the meantime, the signal from the second NAND gate is also inverted by an inverter, and is supplied as an internal clock to the data input portion, data processing portion, and data output portion.

摘要翻译： 半导体集成电路包括具有第一积分部和第二积分部的积分电路。 半导体集成电路还包括数据输入部分，数据处理部分和数据输出部分。 时钟信号由输入缓冲器反相，并与掩模信号一起施加到NAND门。 当来自NAND门的信号上升时，由于积分电路，第二积分部分的信号落在延迟时间之后。 来自NAND门的信号与来自第二积分部分的信号一起施加到第二NAND门，并且来自第二NAND门的信号在从时钟信号上升的时间段期间固定为“L” 在积分电路的延迟时间的持续时间内。 来自第二NAND门的信号被第三积分部分延迟，并且第三积分部分的延迟时间由与门相加以产生掩模信号。 同时，来自第二NAND门的信号也被反相器反相，并作为内部时钟提供给数据输入部分，数据处理部分和数据输出部分。

公开(公告)号：US4951258A

公开(公告)日：1990-08-21

申请号：US375685

申请日：1989-07-05

申请人： Hidenori Uehara

发明人： Hidenori Uehara

IPC分类号： G11C8/06 ,  G11C8/18 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/406 ,  G11C8/06 ,  G11C8/18

摘要： A dynamic random access memory system comprising a memory cell matrix, a row address decoder connected to the memory matrix and a counter for producing internal address signals to refresh the cells of the memory cell matrix. A row address buffer converts the external address signals to row address signals in response to an address buffer enabling signal, and a switching circuit connected to the counter and the row address buffer is selectively switching between the counter and the row address buffer in response to an address switching signal. A decoder circuit connected to the output of the switching circuit decodes selected address signals and provides decoded address signals to the row address decoder. A first control circuit connected to the row address buffer provides the address buffer enabling signal to the row address buffer in response to a row address strobe signal, and a second control circuit provides the address switching signal to the switching circuit in response to the row address strobe signal and a column address strobe signal.

摘要翻译： 一种动态随机存取存储器系统，包括存储单元矩阵，连接到存储器矩阵的行地址解码器和用于产生内部地址信号的计数器，以刷新存储单元矩阵的单元。 行地址缓冲器响应于地址缓冲器使能信号将外部地址信号转换为行地址信号，并且连接到计数器和行地址缓冲器的切换电路响应于一个地址缓冲器选择性地在计数器和行地址缓冲器之间切换 地址切换信号。 连接到开关电路的输出的解码器电路解码所选择的地址信号，并将解码的地址信号提供给行地址解码器。 连接到行地址缓冲器的第一控制电路响应于行地址选通信号向地址缓冲器提供地址缓冲器使能信号，并且第二控制电路响应于行地址向切换电路提供地址切换信号 选通信号和列地址选通信号。

公开(公告)号：US20110204795A1

公开(公告)日：2011-08-25

申请号：US13028293

申请日：2011-02-16

申请人： Hidenori Uehara

发明人： Hidenori Uehara

IPC分类号： H05B37/02

CPC分类号： G09G3/3413 ,  G09G2310/0235 ,  G09G2320/064 ,  G09G2320/0666 ,  G09G2360/145

摘要： A light emission driving device sequentially on a time division basis drives a red light source 200R, a green light source 200G, and a blue light source 200B, to calculate a light emission amount control parameter PWM(k+1) for setting the light emission amount for one of the light sources. The following values are used: a detected light emission amount DET(k) detected for a previous illumination of the same light source, a predetermined value REF(k+1) for comparison to the detected light emission amount DET(k), and the light emission amount control parameters PWM(k) for a previous illumination of the same light source.

摘要翻译： 顺时针方向的发光驱动装置驱动红色光源200R，绿色光源200G和蓝色光源200B，以计算用于设定发光的发光量控制参数PWM（k + 1） 一个光源的数量。 使用以下值：对于相同光源的先前照明检测到的检测到的发光量DET（k），用于与检测到的发光量DET（k）进行比较的预定值REF（k + 1），以及 相同光源的先前照明的发光量控制参数PWM（k）。

公开(公告)号：US06262934B1

公开(公告)日：2001-07-17

申请号：US09551942

申请日：2000-04-19

申请人： Hidenori Uehara

发明人： Hidenori Uehara

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A memory circuit includes a memory cell array having word lines, bit lines and memory cells, and a word line reset circuit for applying an activation level to a word line that is selected, and for applying a lower level which is lower than a deactivation level to the word line when it is non-selected. The word line reset circuit includes a first driver for applying the activation level to the selected word line during a first selected period, a second driver for applying the deactivation level to the word line during a second select period after the first select period, and a third driver for applying the lower level to the word line during a period other than the first and second select periods.

摘要翻译： 存储器电路包括具有字线，位线和存储单元的存储单元阵列和用于将激活电平施加到所选字线的字线复位电路，并且用于施加低于去激活电平的较低电平 到未被选中的字线。 字线复位电路包括：第一驱动器，用于在第一选择周期期间将激活电平施加到所选择的字线;第二驱动器，用于在第一选择周期之后的第二选择周期期间将去激活电平应用于字线;以及 第三驱动器，用于在除了第一和第二选择周期之外的时段期间将低级别应用于字线。

公开(公告)号：US6016070A

公开(公告)日：2000-01-18

申请号：US743363

申请日：1996-11-04

申请人： Hidenori Uehara

发明人： Hidenori Uehara

IPC分类号： G04G3/02 ,  G11C7/00 ,  H03K5/06 ,  H03K5/1252 ,  H03K5/00 ,  H03K3/017

CPC分类号： H03K5/06

摘要： The present invention provides a timing circuit for outputting a signal having an amplified pulse width when a signal having a normal pulse width is inputted thereto, characterized in that when glitch noise whose pulse width is small, is inputted to the timing circuit, a signal having a waveform corresponding to the pulse width thereof is outputted from the timing circuit. The timing circuit comprises a first delay circuit whose input is connected to an input terminal, a first NAND circuit having a first input terminal connected to the first delay circuit and a second input terminal connected to the input terminal, a second delay circuit whose input is connected to the output of the NAND circuit, an inverter whose input is connected to the input terminal, and a second NAND circuit having a first input terminal connected to the output of the second delay circuit and a second input terminal connected to the output of the inverter.

摘要翻译： 本发明提供一种定时电路，用于当输入具有正常脉冲宽度的信号时，输出具有放大脉冲宽度的信号，其特征在于，当脉冲宽度小的脉冲噪声被输入到定时电路时，具有 从其定时电路输出对应于其脉冲宽度的波形。 定时电路包括其输入连接到输入端的第一延迟电路，具有连接到第一延迟电路的第一输入端和连接到输入端的第二输入端的第一NAND电路，其输入为 连接到NAND电路的输出，其输入端连接到输入端的反相器，以及具有连接到第二延迟电路的输出的第一输入端的第二NAND电路和连接到第二延迟电路的输出的第二输入端 逆变器。

公开(公告)号：US5177586A

公开(公告)日：1993-01-05

申请号：US818803

申请日：1992-01-09

申请人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Sanpei Miyamoto ,  Hidenori Uehara

发明人： Tamihiro Ishimura ,  Masahumi Miyawaki ,  Sanpei Miyamoto ,  Hidenori Uehara

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108

CPC分类号： H01L27/0921 ,  G11C11/4074 ,  G11C11/4091 ,  G11C7/065 ,  H01L27/088

摘要： A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

公开(公告)号：US08624886B2

公开(公告)日：2014-01-07

申请号：US13028293

申请日：2011-02-16

申请人： Hidenori Uehara

发明人： Hidenori Uehara

IPC分类号： G09G5/00

CPC分类号： G09G3/3413 ,  G09G2310/0235 ,  G09G2320/064 ,  G09G2320/0666 ,  G09G2360/145

摘要： A light emission driving device sequentially on a time division basis drives a red light source (200R), a green light source (200G), and a blue light source (200B), to calculate a light emission amount control parameter (PWM(k+1)) for setting the light emission amount for one of the light sources. The following values are used: a detected light emission amount (DET(k)) detected for a previous illumination of the same light source, a predetermined value (REF(k+1)) for comparison to the detected light emission amount (DET(k)), and the light emission amount control parameters (PWM(k)) for a previous illumination of the same light source.

摘要翻译： 按照时分依次驱动发光驱动装置驱动红色光源（200R），绿色光源（200G）和蓝色光源（200B），以计算发光量控制参数（PWM（k + 1）），用于设定一个光源的发光量。 使用以下值：对于相同光源的先前照明检测到的检测到的发光量（DET（k）），与检测到的发光量（DET（k + 1））进行比较的预定值（REF（k + 1）） k））和相同光源的先前照明的发光量控制参数（PWM（k））。

公开(公告)号：US06091095A

公开(公告)日：2000-07-18

申请号：US362550

申请日：1999-07-28

申请人： Tadahiro Omata ,  Hidenori Uehara ,  Yuki Hashimoto ,  Shinya Takahashi

发明人： Tadahiro Omata ,  Hidenori Uehara ,  Yuki Hashimoto ,  Shinya Takahashi

IPC分类号： G11C11/409 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  H01L27/08

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line /BL, a second transistor having the drain thereof connected to the bit line /BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.

摘要翻译： 用于放大成对位线之间的电位差的读出放大器具有第一晶体管，其漏极连接到位线BL，其栅极连接到位线/ BL，第二晶体管的漏极连接到位线 BL和其连接到位线BL的栅极，以及与第一和第二晶体管相关联地设置的第三晶体管和第四晶体管，将相同的读出放大器启动信号施加到其栅极。

公开(公告)号：US06304508B1

公开(公告)日：2001-10-16

申请号：US09519573

申请日：2000-03-06

申请人： Hidenori Uehara ,  Nobutaka Nasu

发明人： Hidenori Uehara ,  Nobutaka Nasu

IPC分类号： G11C700

CPC分类号： G11C5/145 ,  G11C8/08

摘要： A semiconductor device includes an internal source voltage generating circuit (debooster circuit) provided between an external source voltage EVCC and a ground voltage VSS and for generating an internal source voltage IVCC necessary to drive each of internal circuits in the semiconductor device, a booster circuit provided between the internal source voltage IVCC and the ground voltage VSS, for generating a boosted voltage VBST higher than the internal source voltage IVCC, and a capacitor provided between the boosted voltage VBST and the ground voltage, for stabilizing the boosted voltage VBST. The capacitor comprises a P type semiconductor substrate to which the ground voltage is applied, and an N type well region having therein a P type well region with a memory cell formed therein and to which the internal source voltage IVCC is applied.

摘要翻译： 半导体器件包括设置在外部源电压EVCC和接地电压VSS之间的内部源极电压发生电路（去激励电路），并且用于产生驱动半导体器件中的每个内部电路所需的内部源极电压IVCC，提供的升压电路 在内部源极电压IVCC和接地电压VSS之间产生用于产生比内部源极电压IVCC高的升压电压VBST，以及设置在升压电压VBST和接地电压之间的电容器，用于稳定升压电压VBST。 电容器包括施加接地电压的P型半导体衬底和其中具有存储单元的P型阱区的N型阱区，并且施加有内部源极电压IVCC。