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公开(公告)号：US07694281B2
公开(公告)日：2010-04-06
申请号：US11241527
申请日：2005-09-30
申请人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
发明人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.
摘要翻译： 确定程序的第一个潜在的热迹。 确定程序的第二个潜在的热迹。 选择第一个潜在热痕迹和第二个潜在热痕迹的常见路径作为程序的选定热痕迹。
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2.发明授权Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints 有权用于动态二进制转换器的装置和方法，以最小的优化约束来支持精确异常公开(公告)号：US07757221B2
公开(公告)日：2010-07-13
申请号：US11241610
申请日：2005-09-30
IPC分类号： G06F9/45
CPC分类号： G06F9/45516 , G06F8/443
摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.
摘要翻译： 一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。 在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。 在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。 在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。 在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。 描述和要求保护其他实施例。
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公开(公告)号：US20090172713A1
公开(公告)日：2009-07-02
申请号：US11968055
申请日：2007-12-31
CPC分类号： G06F9/30145 , G06F9/4552
摘要： Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.
摘要翻译： 方法和设备通过用户级异常处理实现按需指令仿真。 不支持的指令在程序运行时触发异常。 响应于异常，启动用户级或应用程序级异常处理程序，而不是内核级处理程序。 然后异常处理程序可以在应用程序层而不是内核级别执行。 处理程序标识指令并模拟指令，其中指令的仿真由处理程序支持。 仿真指令使程序能够继续执行。 重复的指令仿真通过热代码的动态二进制转换进行分摊。
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公开(公告)号：US08146106B2
公开(公告)日：2012-03-27
申请号：US11968055
申请日：2007-12-31
CPC分类号： G06F9/30145 , G06F9/4552
摘要： Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.
摘要翻译： 方法和设备通过用户级异常处理实现按需指令仿真。 不支持的指令在程序运行时触发异常。 响应于异常，启动用户级或应用程序级异常处理程序，而不是内核级处理程序。 然后异常处理程序可以在应用程序层而不是内核级别执行。 处理程序标识指令并模拟指令，其中指令的仿真由处理程序支持。 仿真指令使程序能够继续执行。 重复的指令仿真通过热代码的动态二进制转换进行分摊。
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公开(公告)号：US07725887B2
公开(公告)日：2010-05-25
申请号：US11020340
申请日：2004-12-22
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： In a method for reducing code size, replaceable subsets of instructions at first locations in areas of infrequently executed instructions in a set of instructions and target subsets of instructions at second locations in the set of instructions are identified, wherein each replaceable subset matches at least one target subset. If multiple target subsets of instructions match one replaceable subset of instructions, one of the multiple matching target subsets is chosen as the matching target subset for the one replaceable subset based on whether the multiple target subsets are located in regions of frequently executed code. For each of at least some of the replaceable subsets of instructions, the replaceable subset of instructions is replaced with an instruction to cause the matching target subset of instructions at the second location to be executed.
摘要翻译： 在减少代码大小的方法中，识别在一组指令中的不经常执行的指令的区域中的第一位置处的指令的可替换子集，以及指令集中的第二位置处的目标指令子集，其中每个可替换子集与至少一个 目标子集。 如果指令的多个目标子集匹配一个可替换的指令子集，则基于多个目标子集是否位于经常执行的代码的区域中，将多个匹配目标子集中的一个选择为一个可替换子集的匹配目标子集。 对于至少一些可替换的指令子集中的每一个，可替换的指令子集被替换为使得执行第二位置处的指令的匹配目标子集的指令。
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6.发明授权Continuous trip count profiling for loop optimizations in two-phase dynamic binary translators 失效在两相动态二进制转换器中循环优化的连续行程计数分析公开(公告)号：US07428731B2
公开(公告)日：2008-09-23
申请号：US10816248
申请日：2004-03-31
CPC分类号： G06F9/45525
摘要： A method, machine readable medium, and system are disclosed. In one embodiment the method comprises collecting a loop trip count continuously during runtime of a region of code being executed that contains a loop, categorizing the trip count to identify one or more code modification techniques applicable to the loop, and dynamically applying the one or more applicable code modification techniques to alter the code that relates to the loop.
摘要翻译： 公开了一种方法，机器可读介质和系统。 在一个实施例中，该方法包括在包含循环的正在执行的代码区域的运行时期期间连续地收集循环行程计数，对行程计数进行分类，以识别适用于循环的一个或多个代码修改技术，以及动态地应用一个或多个 适用的代码修改技术来改变与循环相关的代码。
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公开(公告)号：US07430574B2
公开(公告)日：2008-09-30
申请号：US10877931
申请日：2004-06-24
申请人： Mauricio Breternitz, Jr. , Youfeng Wu , Tal Abir
发明人： Mauricio Breternitz, Jr. , Youfeng Wu , Tal Abir
IPC分类号： G06F7/00
CPC分类号： G06F7/74
摘要： Methods are disclosed to implement bit scan operations using properties of two's complement arithmetic and compute zero index instructions. A data value may be provided and the most-significant or least-significant bit may be determined using the methods set forth herein.
摘要翻译： 公开了使用二进制补码运算和计算零索引指令的特性实现位扫描操作的方法。 可以提供数据值，并且可以使用本文所阐述的方法来确定最高有效位或最低有效位。
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公开(公告)号：US08443353B2
公开(公告)日：2013-05-14
申请号：US12890639
申请日：2010-09-25
申请人： Mauricio Breternitz, Jr. , Youfeng Wu , Cheng Wang , Edson Borin , Shiliang Hu , Craig B. Zilles
发明人： Mauricio Breternitz, Jr. , Youfeng Wu , Cheng Wang , Edson Borin , Shiliang Hu , Craig B. Zilles
IPC分类号： G06F9/45
摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
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公开(公告)号：US07620781B2
公开(公告)日：2009-11-17
申请号：US11642314
申请日：2006-12-19
申请人： Mauricio Breternitz, Jr. , Youfeng Wu , Peter G. Sassone , Jeffrey P. Rupley, II , Wesley Attrot , Bryan Black
发明人： Mauricio Breternitz, Jr. , Youfeng Wu , Peter G. Sassone , Jeffrey P. Rupley, II , Wesley Attrot , Bryan Black
IPC分类号： G06F12/0026
CPC分类号： G06F12/0864 , Y10S707/99943
摘要： Implementation of a Bloom filter using multiple single-ported memory slices. A control value is combined with a hashed address value such that the resultant address value has the property that one, and only one, of the k memories or slices is selected for a given input value, a, for each bank. Collisions are thereby avoided and the multiple hash accesses for a given input value, a, may be performed concurrently. Other embodiments are also described and claimed.
摘要翻译： 使用多个单端口存储器片的Bloom过滤器的实现。 控制值与散列地址值组合，使得所得到的地址值具有对于每个存储体的给定输入值a选择k个存储器或片中仅一个且仅一个的属性。 因此避免了冲突，并且可以同时执行给定输入值a的多个哈希访问。 还描述和要求保护其他实施例。
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公开(公告)号：US07095342B1
公开(公告)日：2006-08-22
申请号：US11096152
申请日：2005-03-31
IPC分类号： H03M7/40
CPC分类号： H03M7/3084
摘要： In one embodiment, the present invention includes a method to compress data stored in a memory to reduce size and power consumption. The method includes segmenting each word of a code portion into multiple fields, forming tables having unique entries for each of the fields, and assigning a pointer to each of the unique entries in each of the tables. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种压缩存储在存储器中的数据以减小尺寸和功率消耗的方法。 该方法包括将代码部分的每个字段分割成多个字段，形成具有用于每个字段的唯一条目的表，并且将指针分配给每个表中的每个唯一条目。 描述和要求保护其他实施例。
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