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公开(公告)号：US07692946B2
公开(公告)日：2010-04-06
申请号：US11771054
申请日：2007-06-29
申请人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
发明人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。
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公开(公告)号：US07171545B2
公开(公告)日：2007-01-30
申请号：US10747625
申请日：2003-12-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30138
摘要： A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.
摘要翻译： 支持预测寄存器高速缓存分配和输入的机制使用计数器查找表来确定物理寄存器引用的潜在重要性。
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3.发明授权公开(公告)号：US07130990B2
公开(公告)日：2006-10-31
申请号：US10334528
申请日：2002-12-31
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.
摘要翻译： 提供了一种用于向调度器提供就绪信息的方法和装置。 依赖信息保存在相对较小的地图表中，当依赖信息超过地图表中的可用空间时，可能会丢失信息。 在选择队列中，随着空间允许，维护就绪指令。 调度指令的标签保存在查找队列中，并且随着空间允许，调度指令的依赖关系信息保持在更新队列中。 基于更新队列中的信息更新调度窗口中的指令的就绪信息。 由于空间限制，映射表，查找队列，更新队列和/或选择队列可能会导致指令信息丢失。 丢失指令的调度由有损指令处理程序处理。
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4.发明授权Apparatus and method using different size rename registers for partial-bit and bulk-bit writes 有权使用不同大小的重命名寄存器进行部分位和批量位写入的装置和方法公开(公告)号：US07428631B2
公开(公告)日：2008-09-23
申请号：US10632432
申请日：2003-07-31
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30112 , G06F9/384
摘要： An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both partial-bit accesses and bulk-bit accesses to bits of the register. Rename logic utilizes a rename map table associated with the logical register to be renamed and also includes a plurality of physical rename registers. They physical rename registers include a set of skinny physical rename registers to be used for renaming for partial-bit writes. The physical rename registers also include a set of fat physical rename registers to be used for renaming for bulk-bit writes. Additional sizes of physical rename registers may also be employed. The entries of the single physical rename map table may point to either fat or skinny physical rename registers.
摘要翻译： 提供了一种装置和方法，用于重命名允许不同长度的比特访问的逻辑寄存器，例如谓词寄存器。 重命名逻辑支持对部分位访问和对寄存器的位的批量访问进行重命名。 重命名逻辑利用与逻辑寄存器相关联的重命名映射表来重命名，并且还包括多个物理重命名寄存器。 它们的物理重命名寄存器包括一组用于部分位写入重命名的瘦物理重命名寄存器。 物理重命名寄存器还包括一组用于批量位写入重命名的胖物理重命名寄存器。 还可以使用附加大小的物理重命名寄存器。 单个物理重命名映射表的条目可能指向胖或瘦身体重命名寄存器。
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公开(公告)号：US07418551B2
公开(公告)日：2008-08-26
申请号：US10886402
申请日：2004-07-06
IPC分类号： G06F12/00
CPC分类号： G06F9/3826 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F12/0875 , Y02D10/13
摘要： A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.
摘要翻译： 如果注册文件资源不可用，则使用可用的注册缓存资源的技术。 如果寄存器文件写入端口或空间不可用，本发明的实施例涉及用于将写回数据存储到寄存器高速缓存的寄存器高速缓存回写算法。
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公开(公告)号：US08059441B2
公开(公告)日：2011-11-15
申请号：US12709620
申请日：2010-02-22
申请人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
发明人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。
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公开(公告)号：US20100149849A1
公开(公告)日：2010-06-17
申请号：US12709620
申请日：2010-02-22
申请人： Mohammed Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
发明人： Mohammed Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。
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公开(公告)号：US07620781B2
公开(公告)日：2009-11-17
申请号：US11642314
申请日：2006-12-19
申请人： Mauricio Breternitz, Jr. , Youfeng Wu , Peter G. Sassone , Jeffrey P. Rupley, II , Wesley Attrot , Bryan Black
发明人： Mauricio Breternitz, Jr. , Youfeng Wu , Peter G. Sassone , Jeffrey P. Rupley, II , Wesley Attrot , Bryan Black
IPC分类号： G06F12/0026
CPC分类号： G06F12/0864 , Y10S707/99943
摘要： Implementation of a Bloom filter using multiple single-ported memory slices. A control value is combined with a hashed address value such that the resultant address value has the property that one, and only one, of the k memories or slices is selected for a given input value, a, for each bank. Collisions are thereby avoided and the multiple hash accesses for a given input value, a, may be performed concurrently. Other embodiments are also described and claimed.
摘要翻译： 使用多个单端口存储器片的Bloom过滤器的实现。 控制值与散列地址值组合，使得所得到的地址值具有对于每个存储体的给定输入值a选择k个存储器或片中仅一个且仅一个的属性。 因此避免了冲突，并且可以同时执行给定输入值a的多个哈希访问。 还描述和要求保护其他实施例。
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9.发明授权
公开(公告)号：US6157999A
公开(公告)日：2000-12-05
申请号：US868467
申请日：1997-06-03
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3844 , G06F9/4426
摘要： When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When the information is not updated, a predicted address is provided to the prediction verifier (460) by the link stack (410). Once the busy bit is valid, the prediction verifier (460) determines if a proper prediction was made. When an improper prediction was made, the update portion (415) of the link stack (410) based on information from the comparator (425) determines if a value stored in the link stack (410) matches the value stored in the return memory location (440). The link stack (410) is synchronized based upon a favorable comparison indicating the return memory location value matches a value in the link stack. If a match is not found, the predicted address is placed back on the link stack or alternatively the link stack is cleared.
摘要翻译： 当发生分支到存储在返回存储器位置（440）中的地址的请求时，使用忙位来确定返回存储器位置（440）是否包含更新的信息。 当不更新信息时，通过链路栈（410）将预测地址提供给预测验证器（460）。 一旦忙位有效，预测验证器（460）确定是否进行了适当的预测。 当进行不正确的预测时，基于来自比较器（425）的信息，链接堆栈（410）的更新部分（415）确定存储在链接堆栈（410）中的值是否与存储在返回存储器位置中的值相匹配 （440）。 基于指示返回存储器位置值与链路栈中的值匹配的有利比较，链路栈（410）被同步。 如果没有找到匹配项，则将预测的地址放回到链路栈，或者链路栈被清除。
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公开(公告)号：US09977674B2
公开(公告)日：2018-05-22
申请号：US10685654
申请日：2003-10-14
CPC分类号： G06F9/30043 , G06F9/30072 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.
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