公开(公告)号：US06590421B2

公开(公告)日：2003-07-08

申请号：US10101475

申请日：2002-03-19

申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim ,  Il-Won Seo ,  Moo-Sung Chae

发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim ,  Il-Won Seo ,  Moo-Sung Chae

IPC分类号： H03K190175

CPC分类号： H03K19/00323

摘要： A semiconductor capable of reducing skew between plural-bit output data by using a plurality of data output drivers and a method thereof. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state in response to signals received from other data output drivers.

公开(公告)号：US20050108607A1

公开(公告)日：2005-05-19

申请号：US10954870

申请日：2004-09-29

申请人： Moo-Sung Chae ,  Hye-In Choi

发明人： Moo-Sung Chae ,  Hye-In Choi

IPC分类号： G11C29/14 ,  G01R31/28 ,  G06F11/00 ,  G11C29/00 ,  G11C29/34 ,  G11C29/36

CPC分类号： G11C29/36 ,  G11C2029/3602

摘要： A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.

摘要翻译： 半导体存储器件包括：模式设置寄存器，用于响应于模式设置命令，根据外部施加的模式设置寄存器代码生成并行位测试信号和代码; 数据输入电路，用于响应写入命令接收和输出外部施加的数据的至少一位; 以及测试图形数据产生电路，用于从代码接收并行比特测试信号和预定比特，以响应于从数据输入电路接收的外部施加的数据的至少一个比特生成测试图形数据。

公开(公告)号：US07539826B2

公开(公告)日：2009-05-26

申请号：US11117804

申请日：2005-04-29

申请人： Moo-Sung Chae ,  Kye-Hyun Kyung

发明人： Moo-Sung Chae ,  Kye-Hyun Kyung

IPC分类号： G06F12/16

CPC分类号： G06F11/1666 ,  G06F11/2056 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1045

摘要： By using the combination of a pre-existing command signal that is common to two memory devices and a non-shared command signal that is applied individually to each of the devices, embodiments of the invention may operate in a mirror mode, thereby preventing unwanted signal degradation due to stub loads. Because embodiments of the invention do not require additional dedicated pins and/or pads compared to the conventional art, it is possible to achieve mirror mode operation in a smaller device package.

摘要翻译： 通过使用两个存储器件共有的预先存在的命令信号的组合和单独应用于每个器件的非共享命令信号，本发明的实施例可以以镜像模式操作，从而防止不必要的信号 由于存根负载导致的退化。 由于与传统技术相比，本发明的实施例不需要额外的专用引脚和/或焊盘，所以可以在较小的器件封装中实现镜像模式操作。

公开(公告)号：US07257754B2

公开(公告)日：2007-08-14

申请号：US10954870

申请日：2004-09-29

申请人： Moo-Sung Chae ,  Hye-In Choi

发明人： Moo-Sung Chae ,  Hye-In Choi

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G11C29/36 ,  G11C2029/3602

摘要： A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.

摘要翻译： 半导体存储器件包括：模式设置寄存器，用于响应于模式设置命令，根据外部施加的模式设置寄存器代码生成并行位测试信号和代码; 数据输入电路，用于响应写入命令接收和输出外部施加的数据的至少一位; 以及测试图形数据产生电路，用于从代码接收并行比特测试信号和预定比特，以响应于从数据输入电路接收的外部施加的数据的至少一个比特生成测试图形数据。

公开(公告)号：US20050262318A1

公开(公告)日：2005-11-24

申请号：US11117804

申请日：2005-04-29

申请人： Moo-Sung Chae ,  Kye-Hyun Kyung

发明人： Moo-Sung Chae ,  Kye-Hyun Kyung

IPC分类号： H01L25/00 ,  G06F12/16

CPC分类号： G06F11/1666 ,  G06F11/2056 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1045

摘要： By using the combination of a pre-existing command signal that is common to two memory devices and a non-shared command signal that is applied individually to each of the devices, embodiments of the invention may operate in a mirror mode, thereby preventing unwanted signal degradation due to stub loads. Because embodiments of the invention do not require additional dedicated pins and/or pads compared to the conventional art, it is possible to achieve mirror mode operation in a smaller device package.

摘要翻译： 通过使用两个存储器件共有的预先存在的命令信号的组合和单独应用于每个器件的非共享命令信号，本发明的实施例可以以镜像模式操作，从而防止不必要的信号 由于存根负载导致的退化。 由于与传统技术相比，本发明的实施例不需要额外的专用引脚和/或焊盘，所以可以在较小的器件封装中实现镜像模式操作。