公开(公告)号：US06392456B1

公开(公告)日：2002-05-21

申请号：US09427272

申请日：1999-10-26

申请人： Hong Beom Pyeon ,  Kyung Hoon Chang ,  Ju Han Kim

发明人： Hong Beom Pyeon ,  Kyung Hoon Chang ,  Ju Han Kim

IPC分类号： H03L706

CPC分类号： H03L7/0814 ,  Y10S331/02

摘要： An analog mixed digital DLL includes a digital mode controller and an analog mode controller. The digital mode controller compares phases of delay clock signals outputted from a plurality of delay blocks and a first clock signal, detects an initial locking point, selects one delay clock signal at the detected initial locking point and controls the operation of the delay clocks. The analog mode controller compares the phase of the delay clock signal selected by the digital mode controller and the phase of a first clock signal. The analog mixed digital DLL can provide an externally inputted first control voltage or a second control voltage to the delay blocks in accordance with the digital and analog operation modes and implements a wide band frequency operation, has a short duration of jitters, prevents a multi-locking during a wide band frequency operation and decreases a current consumption.

摘要翻译： 模拟混合数字DLL包括数字模式控制器和模拟模式控制器。 数字模式控制器比较从多个延迟块输出的延迟时钟信号和第一时钟信号的相位，检测初始锁定点，在检测到的初始锁定点选择一个延迟时钟信号，并控制延迟时钟的操作。 模拟模式控制器比较由数字模式控制器选择的延迟时钟信号的相位和第一时钟信号的相位。 模拟混合数字DLL可以根据数字和模拟操作模式向延迟块提供外部输入的第一控制电压或第二控制电压，并且实现宽带频率操作，具有短暂的抖动持续时间， 在宽带频率操作期间锁定并且减少电流消耗。

公开(公告)号：US06337816B1

公开(公告)日：2002-01-08

申请号：US09578865

申请日：2000-05-26

申请人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

发明人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C29/785

摘要： The present invention relates to a column redundancy circuit for a semiconductor memory whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the normal memory cells and the redundancy data stored in the redundancy memory cells are outputted to a switch unit. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the normal data or redundancy data from the memory array, and outputs it to a main amplifier.

摘要翻译： 本发明涉及一种用于半导体存储器的列冗余电路，其存储器阵列被划分成多个阵列单元，以便以高频适当地工作。 存储器阵列中的多个阵列单元包括多个正常存储单元和多个冗余存储单元。 存储在正常存储单元中的正常数据和存储在冗余存储单元中的冗余数据被输出到开关单元。 列冗余单元根据列地址，行地址和熔丝短路状态输出冗余使能信号。 根据冗余使能信号的逻辑状态，开关单元从存储器阵列中选择正常数据或冗余数据，并将其输出到主放大器。

公开(公告)号：US06343037B1

公开(公告)日：2002-01-29

申请号：US09625642

申请日：2000-07-25

申请人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

发明人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C29/785

摘要： The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the plurality of normal memory cells and the redundancy data stored in the plurality of redundancy memory cells are outputted through a local normal input/output line and a local redundancy input/output line, respectively. The column redundancy unit outputs a redundancy enable signal according to a column address, a row address, and a state of a fuse. The normal data stored in the plurality of normal memory cells or the redundancy data stored in the plurality of redundancy memory cells is selected according to a logical state of the redundancy enable signal, and outputted to a main amplifier via a global input/output line.

摘要翻译： 本发明涉及一种用于半导体存储器的列冗余电路，其可以促进将其存储阵列分成多个阵列单元的高集成半导体电路，以便以高频适当地操作。 存储器阵列中的多个阵列单元包括多个正常存储单元和多个冗余存储单元。 存储在多个正常存储单元中的常规数据和存储在多个冗余存储单元中的冗余数据分别通过本地通用输入/输出线和本地冗余输入/输出线输出。 列冗余单元根据列地址，行地址和保险丝的状态输出冗余使能信号。 存储在多个正常存储单元中的正常数据或存储在多个冗余存储单元中的冗余数据根据冗余使能信号的逻辑状态来选择，并通过全局输入/输出线输出到主放大器。

公开(公告)号：US06172921B2

公开(公告)日：2001-01-09

申请号：US09426725

申请日：1999-10-26

申请人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

发明人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

IPC分类号： G11C2900

CPC分类号： G11C29/846 ,  G11C29/785

摘要： The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The redundancy data stored in the redundancy memory cells are outputted to a first main amplifier, and the normal data stored in the normal memory cells are outputted to a second main amplifier. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the redundancy data from the first main amplifier or the normal data from the second amplifier, and outputs it to a data output buffer.

摘要翻译： 本发明涉及一种用于半导体存储器的列冗余电路，其可以促进将其存储阵列分成多个阵列单元的高集成半导体电路，以便以高频适当地操作。 存储器阵列中的多个阵列单元包括多个正常存储单元和多个冗余存储单元。 存储在冗余存储单元中的冗余数据被输出到第一主放大器，并且存储在正常存储单元中的正常数据被输出到第二主放大器。 列冗余单元根据列地址，行地址和熔丝短路状态输出冗余使能信号。 根据冗余使能信号的逻辑状态，开关单元选择来自第一主放大器的冗余数据或来自第二放大器的正常数据，并将其输出到数据输出缓冲器。

公开(公告)号：US20120294439A1

公开(公告)日：2012-11-22

申请号：US13474655

申请日：2012-05-17

申请人： Doo Ho CHOI ,  Yong-Je Choi ,  You Sung Kang ,  Ju Han Kim ,  Tae sung Kim ,  Kyung hee Oh

发明人： Doo Ho CHOI ,  Yong-Je Choi ,  You Sung Kang ,  Ju Han Kim ,  Tae sung Kim ,  Kyung hee Oh

IPC分类号： G06F21/24

CPC分类号： G06F21/755

摘要： Disclosed is a method for implementing a symmetric key encryption algorithm against power analysis attacks, including: generating and storing an affine transform table; generating and storing a masked inversion table; and operating a masked S-box using the affine transform table and the masked inversion table.

摘要翻译： 公开了一种实现针对功率分析攻击的对称密钥加密算法的方法，包括：生成和存储仿射变换表; 生成和存储掩蔽的反转表; 并使用仿射变换表和掩蔽的反转表来操作屏蔽的S盒。

公开(公告)号：US08085352B2

公开(公告)日：2011-12-27

申请号：US12289024

申请日：2008-10-17

申请人： Ju Han Kim ,  Jong Beom Lee

发明人： Ju Han Kim ,  Jong Beom Lee

IPC分类号： G02F1/1333

CPC分类号： H01L27/0248 ,  G02F1/136204

摘要： A width and a length of the electrostatic discharge (ESD) protection circuit are reduced by changing a connection structure of the electrostatic discharge protection circuit. The ESD protection circuit includes a plurality of gate electrodes disposed between odd signal lines and even signal lines adjacent to the odd signal lines among the signal lines; source/drain electrode pairs each disposed on a respective one of the gate electrodes to form a plurality of transistors; and connection nodes parallel to the source/drain electrode pairs, each connection node adjacent to a respective one of the source/drain electrodes pairs and on a respective one of the gate electrodes, wherein each of the connection nodes is directly connected to the source/drain electrode pair of an adjacent transistor and the gate electrode formed below the source/drain electrode through a contact part.

摘要翻译： 通过改变静电放电保护电路的连接结构来减小静电放电（ESD）保护电路的宽度和长度。 ESD保护电路包括设置在信号线之间的奇数信号线和与奇数信号线相邻的偶数信号线之间的多个栅电极; 源极/漏极电极对，各自设置在相应的一个栅电极上以形成多个晶体管; 以及与源/漏电极对平行的连接节点，每个连接节点与源/漏电极对中的相应一个相邻并且在相应的一个栅电极上，其中每个连接节点直接连接到源/ 相邻晶体管的漏电极对和通过接触部分形成在源/漏电极下方的栅电极。

公开(公告)号：US20090102995A1

公开(公告)日：2009-04-23

申请号：US12289024

申请日：2008-10-17

申请人： Ju Han Kim ,  Jong Beom Lee

发明人： Ju Han Kim ,  Jong Beom Lee

IPC分类号： G02F1/133 ,  H02H3/20 ,  H01L21/70

CPC分类号： H01L27/0248 ,  G02F1/136204

摘要： A width and a length of the electrostatic discharge (ESD) protection circuit are reduced by changing a connection structure of the electrostatic discharge protection circuit. The ESD protection circuit includes a plurality of gate electrodes disposed between odd signal lines and even signal lines adjacent to the odd signal lines among the signal lines; source/drain electrode pairs each disposed on a respective one of the gate electrodes to form a plurality of transistors; and connection nodes parallel to the source/drain electrode pairs, each connection node adjacent to a respective one of the source/drain electrodes pairs and on a respective one of the gate electrodes, wherein each of the connection nodes is directly connected to the source/drain electrode pair of an adjacent transistor and the gate electrode formed below the source/drain electrode through a contact part.

摘要翻译： 通过改变静电放电保护电路的连接结构来减小静电放电（ESD）保护电路的宽度和长度。 ESD保护电路包括设置在信号线之间的奇数信号线和与奇数信号线相邻的偶数信号线之间的多个栅电极; 源极/漏极电极对，各自设置在相应的一个栅电极上以形成多个晶体管; 以及与源/漏电极对平行的连接节点，每个连接节点与源/漏电极对中的相应一个相邻并且在相应的一个栅电极上，其中每个连接节点直接连接到源/ 相邻晶体管的漏电极对和通过接触部分形成在源/漏电极下方的栅电极。

公开(公告)号：US5881015A

公开(公告)日：1999-03-09

申请号：US915599

申请日：1997-08-21

申请人： Ju Han Kim

发明人： Ju Han Kim

IPC分类号： G11C11/413 ,  G05F1/46 ,  G05F3/24 ,  G05F3/26 ,  G11C5/14 ,  G11C11/407 ,  G11C7/00

CPC分类号： G05F1/465 ,  G11C5/147

摘要： An internal constant voltage control circuit for a semiconductor memory device includes a current source for generating voltage in accordance with current when power is turned on, a bias circuit for outputting a first bias voltage when power is turned on, a first level shifter for receiving the output voltage of the current source and outputting a first voltage, a second level shifter for receiving the output voltage of the bias circuit and outputting a second voltage, and a buffer for differentially amplifying the output voltage of the first level shifter and the output voltage of the second level shifter, and generating an internal voltage. The circuit decreases operation current by reducing an internal voltage during a low temperature operation and securing a timing margin between signals, thereby stabilizing a low temperature operation.

摘要翻译： 一种用于半导体存储器件的内部恒压控制电路，包括：电源接通时根据电流产生电压的电流源;电源接通时用于输出第一偏置电压的偏置电路;第一电平移位器， 电流源的输出电压并输出第一电压，第二电平移位器，用于接收偏置电路的输出电压并输出第二电压;以及缓冲器，用于差分放大第一电平转换器的输出电压和输出电压 第二电平移位器，并产生内部电压。 该电路通过在低温操作期间降低内部电压并且确保信号之间的定时裕度来降低操作电流，从而稳定低温操作。

公开(公告)号：US08774406B2

公开(公告)日：2014-07-08

申请号：US13333324

申请日：2011-12-21

申请人： Yong-Je Choi ,  Doo Ho Choi ,  Taesung Kim ,  Kyunghee Oh ,  You Sung Kang ,  Ju Han Kim ,  Jeong Nyeo Kim ,  Hyun sook Cho

发明人： Yong-Je Choi ,  Doo Ho Choi ,  Taesung Kim ,  Kyunghee Oh ,  You Sung Kang ,  Ju Han Kim ,  Jeong Nyeo Kim ,  Hyun sook Cho

IPC分类号： H04K1/02 ,  H04N7/167 ,  G06F11/00 ,  G06F12/14 ,  G06F12/16 ,  G08B23/00

CPC分类号： H04L9/002 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/12

摘要： A masking addition operation apparatus for prevention of a side channel attack, includes a random value generation unit generating a first random value for a first input, second random value for a second input, and a summation random value. The masking addition operation apparatus includes an operation part performing an operation on the first and second random values, a previous carry input, and first and second masked random values generated based on the first and second random values. The masking addition operation apparatus includes a carry generator generating a carry input using a result of the operation part; and a summation bit generator generating a summation bit using the summation random value, the first and second random values, the previous carry input and the first and second masked random values.

摘要翻译： 一种用于防止侧信道攻击的掩蔽加法运算装置，包括产生用于第一输入的第一随机值，第二输入的第二随机值和求和随机值的随机值生成单元。 掩蔽附加运算装置包括对第一和第二随机值执行操作的操作部分，先前进位输入以及基于第一和第二随机值生成的第一和第二屏蔽随机值。 掩蔽加法运算装置包括使用运算部的结果生成进位输入的进位发生器; 以及求和位发生器，其使用求和随机值，第一和第二随机值，先前进位输入和第一和第二屏蔽随机值产生求和位。

公开(公告)号：US20140107515A1

公开(公告)日：2014-04-17

申请号：US14008795

申请日：2011-08-19

申请人： Byung Hoon Lee ,  Ju Han Kim

发明人： Byung Hoon Lee ,  Ju Han Kim

IPC分类号： A61B7/04 ,  A61B5/00 ,  A61B7/00

CPC分类号： A61B7/04 ,  A61B5/0004 ,  A61B5/7203 ,  A61B5/7225 ,  A61B5/7282 ,  A61B5/741 ,  A61B5/742 ,  A61B7/003 ,  A61B7/008 ,  A61B7/026 ,  G06F19/00

摘要： The present invention relates to a telemedical stethoscope, which automatically diagnoses a disease, and records visually and auditorily, and stores the stethoscope data on a screen. The present invention enhances primary diagnosis and treatment effect for a patient by transmitting/receiving the data to/from a doctor at a medical center and by receiving a telemedicine service. In addition, the present invention transmits the data to a health management program so as to be used for personal healthcare and disease prognosis decision of a patient.

摘要翻译： 本发明涉及一种远程医疗听诊器，其自动诊断疾病，并且在视觉上和听觉上记录并将听诊器数据存储在屏幕上。 本发明通过在医疗中心向医生发送/接收数据并通过接收远程医疗服务来增强患者的初步诊断和治疗效果。 此外，本发明将数据发送到健康管理程序，以便用于患者的个人保健和疾病预后决定。