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    Analog mixed digital DLL
    1.
    发明授权
    Analog mixed digital DLL 有权
    模拟混合数字DLL

    公开(公告)号：US06392456B1

    公开(公告)日：2002-05-21

    申请号：US09427272

    申请日：1999-10-26

    申请人： Hong Beom Pyeon ,  Kyung Hoon Chang ,  Ju Han Kim

    发明人： Hong Beom Pyeon ,  Kyung Hoon Chang ,  Ju Han Kim

    IPC分类号： H03L706

    CPC分类号： H03L7/0814 ,  Y10S331/02

    摘要： An analog mixed digital DLL includes a digital mode controller and an analog mode controller. The digital mode controller compares phases of delay clock signals outputted from a plurality of delay blocks and a first clock signal, detects an initial locking point, selects one delay clock signal at the detected initial locking point and controls the operation of the delay clocks. The analog mode controller compares the phase of the delay clock signal selected by the digital mode controller and the phase of a first clock signal. The analog mixed digital DLL can provide an externally inputted first control voltage or a second control voltage to the delay blocks in accordance with the digital and analog operation modes and implements a wide band frequency operation, has a short duration of jitters, prevents a multi-locking during a wide band frequency operation and decreases a current consumption.

    摘要翻译： 模拟混合数字DLL包括数字模式控制器和模拟模式控制器。 数字模式控制器比较从多个延迟块输出的延迟时钟信号和第一时钟信号的相位，检测初始锁定点，在检测到的初始锁定点选择一个延迟时钟信号，并控制延迟时钟的操作。 模拟模式控制器比较由数字模式控制器选择的延迟时钟信号的相位和第一时钟信号的相位。 模拟混合数字DLL可以根据数字和模拟操作模式向延迟块提供外部输入的第一控制电压或第二控制电压，并且实现宽带频率操作，具有短暂的抖动持续时间， 在宽带频率操作期间锁定并且减少电流消耗。

    Column redundancy circuit for semiconductor memory
    2.
    发明授权
    Column redundancy circuit for semiconductor memory 失效
    半导体存储器的列冗余电路

    公开(公告)号：US06337816B1

    公开(公告)日：2002-01-08

    申请号：US09578865

    申请日：2000-05-26

    申请人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

    发明人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

    IPC分类号： G11C700

    CPC分类号： G11C29/846 ,  G11C29/785

    摘要： The present invention relates to a column redundancy circuit for a semiconductor memory whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the normal memory cells and the redundancy data stored in the redundancy memory cells are outputted to a switch unit. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the normal data or redundancy data from the memory array, and outputs it to a main amplifier.

    摘要翻译： 本发明涉及一种用于半导体存储器的列冗余电路，其存储器阵列被划分成多个阵列单元，以便以高频适当地工作。 存储器阵列中的多个阵列单元包括多个正常存储单元和多个冗余存储单元。 存储在正常存储单元中的正常数据和存储在冗余存储单元中的冗余数据被输出到开关单元。 列冗余单元根据列地址，行地址和熔丝短路状态输出冗余使能信号。 根据冗余使能信号的逻辑状态，开关单元从存储器阵列中选择正常数据或冗余数据，并将其输出到主放大器。

    Column redundancy circuit for semiconductor memory
    3.
    发明授权
    Column redundancy circuit for semiconductor memory 失效
    半导体存储器的列冗余电路

    公开(公告)号：US06343037B1

    公开(公告)日：2002-01-29

    申请号：US09625642

    申请日：2000-07-25

    申请人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

    发明人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

    IPC分类号： G11C700

    CPC分类号： G11C29/846 ,  G11C29/785

    摘要： The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the plurality of normal memory cells and the redundancy data stored in the plurality of redundancy memory cells are outputted through a local normal input/output line and a local redundancy input/output line, respectively. The column redundancy unit outputs a redundancy enable signal according to a column address, a row address, and a state of a fuse. The normal data stored in the plurality of normal memory cells or the redundancy data stored in the plurality of redundancy memory cells is selected according to a logical state of the redundancy enable signal, and outputted to a main amplifier via a global input/output line.

    摘要翻译： 本发明涉及一种用于半导体存储器的列冗余电路，其可以促进将其存储阵列分成多个阵列单元的高集成半导体电路，以便以高频适当地操作。 存储器阵列中的多个阵列单元包括多个正常存储单元和多个冗余存储单元。 存储在多个正常存储单元中的常规数据和存储在多个冗余存储单元中的冗余数据分别通过本地通用输入/输出线和本地冗余输入/输出线输出。 列冗余单元根据列地址，行地址和保险丝的状态输出冗余使能信号。 存储在多个正常存储单元中的正常数据或存储在多个冗余存储单元中的冗余数据根据冗余使能信号的逻辑状态来选择，并通过全局输入/输出线输出到主放大器。

    Column redundancy circuit for semiconductor memory
    4.
    发明授权
    Column redundancy circuit for semiconductor memory 有权
    半导体存储器的列冗余电路

    公开(公告)号：US06172921B2

    公开(公告)日：2001-01-09

    申请号：US09426725

    申请日：1999-10-26

    申请人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

    发明人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

    IPC分类号： G11C2900

    CPC分类号： G11C29/846 ,  G11C29/785

    摘要： The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The redundancy data stored in the redundancy memory cells are outputted to a first main amplifier, and the normal data stored in the normal memory cells are outputted to a second main amplifier. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the redundancy data from the first main amplifier or the normal data from the second amplifier, and outputs it to a data output buffer.

    摘要翻译： 本发明涉及一种用于半导体存储器的列冗余电路，其可以促进将其存储阵列分成多个阵列单元的高集成半导体电路，以便以高频适当地操作。 存储器阵列中的多个阵列单元包括多个正常存储单元和多个冗余存储单元。 存储在冗余存储单元中的冗余数据被输出到第一主放大器，并且存储在正常存储单元中的正常数据被输出到第二主放大器。 列冗余单元根据列地址，行地址和熔丝短路状态输出冗余使能信号。 根据冗余使能信号的逻辑状态，开关单元选择来自第一主放大器的冗余数据或来自第二放大器的正常数据，并将其输出到数据输出缓冲器。

    System having one or more memory devices
    5.
    发明授权
    System having one or more memory devices 有权
    系统具有一个或多个存储器件

    公开(公告)号：US08812768B2

    公开(公告)日：2014-08-19

    申请号：US12033577

    申请日：2008-02-19

    申请人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

    发明人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10 ,  Y02D10/14 ,  Y02D10/151

    摘要： A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

    摘要翻译： 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

    MEMORY SYSTEM WITH A LAYER COMPRISING A DEDICATED REDUNDANCY AREA
    7.
    发明申请
    MEMORY SYSTEM WITH A LAYER COMPRISING A DEDICATED REDUNDANCY AREA 有权
    具有包含专用冗余区域的层的记忆系统

    公开(公告)号：US20130070547A1

    公开(公告)日：2013-03-21

    申请号：US13621486

    申请日：2012-09-17

    申请人： Hong Beom Pyeon

    发明人： Hong Beom Pyeon

    IPC分类号： G11C29/24

    CPC分类号： G11C29/785 ,  G11C29/44 ,  G11C2029/1206 ,  G11C2029/4402

    摘要： Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.

    摘要翻译： 公开了可以包括包括第一冗余存储器元件，输入/输出接口，第一层保险丝盒和保险丝熔断控制的第一层的系统和方法。 这些系统和方法还可以包括通过包括耦合到第一冗余存储器元件的第二层存储器元件和第二层熔丝盒的第一连接耦合到第一层的第二层。 此外，这些系统和方法还可以包括耦合到第一层的冗余寄存器，其中当第二层存储器元件的一部分出现故障时，冗余寄存器向熔丝熔断控制提供信息，其分配第一冗余存储器的一部分 元件，以通过在第一层熔丝盒和第二层熔丝盒中吹入元件来为第二层存储元件的故障部分提供冗余。

    Bridge device architecture for connecting discrete memory devices to a system
    8.
    发明授权
    Bridge device architecture for connecting discrete memory devices to a system 有权
    用于将分立存储器件连接到系统的桥接器件架构

    公开(公告)号：US08363444B2

    公开(公告)日：2013-01-29

    申请号：US13365895

    申请日：2012-02-03

    申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    IPC分类号： G11C7/02

    CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

    摘要： A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

    摘要翻译： 用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括用于连接至少一个分立存储器件的本地控制接口，用于连接至少一个分立存储器件的本地输入/输出接口以及全局输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

    Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
    9.
    发明授权
    Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh 有权
    具有温度补偿自刷新功能的自动刷新存储单元的动态随机存取存储器件和方法

    公开(公告)号：US08300488B2

    公开(公告)日：2012-10-30

    申请号：US12705040

    申请日：2010-02-12

    申请人： Hong Beom Pyeon

    发明人： Hong Beom Pyeon

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4061

    摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

    摘要翻译： 动态随机存取存储器（DRAM）器件具有逐列的DRAM单元阵列。 阵列的每个DRAM单元与相应列的相应行和位线的字线相连。 通过模式检测器检测进入和退出自刷新模式，并提供自刷新模式信号。 响应于自刷新模式信号产生的振荡电路产生基本时间段。 第一分频器/时间周期乘法器根据与DRAM器件有关的过程变化因素来改变基本时间周期。 第二分频器/时间周期乘法器还根据与DRAM器件有关的温度变化因素来改变改变的时间周期。 在自刷新模式下，存储在DRAM单元中的数据被刷新。 根据这两个因素，DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

    DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR
    10.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR 有权
    动态随机存取存储器及其增压电压生产商

    公开(公告)号：US20120069693A1

    公开(公告)日：2012-03-22

    申请号：US13305064

    申请日：2011-11-28

    申请人： Hong Beom Pyeon

    发明人： Hong Beom Pyeon

    IPC分类号： G11C5/14

    CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068 ,  H02M3/073 ,  H02M2003/077

    摘要： A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

    摘要翻译： 动态随机存取存储器（DRAM）可选择性地在睡眠模式和另一模式下操作。 DRAM具有在刷新模式下刷新的数据存储单元。 为DRAM的操作提供升压电压。 升压电压提供器包括一组电荷泵电路，其基于用于在睡眠模式下刷新DRAM单元中的数据的刷新时间由泵控制电路选择性地激活。