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1.发明授权Asynchronous successive-approximation-register analog-to-digital converter (SAR ADC) in synchronized system 有权同步系统中的异步逐次逼近寄存器模数转换器（SAR ADC）公开(公告)号：US09484945B1
公开(公告)日：2016-11-01
申请号：US15146890
申请日：2016-05-05
CPC分类号： H03M1/46 , H03M1/0863 , H03M1/125
摘要： A correcting asynchronous Successive-Approximation Register (SAR) analog-to-digital converter (ADC) detects and corrects metastability errors. An analog signal is synchronously sampled by a system clock, but data bits are converted asynchronously. A valid detector compares true and complement outputs of a comparator that compares the sampled voltage to a DAC voltage generated from digital test value from the SAR. Once the true and complement outputs diverge past logic thresholds, the valid detector activates a VALID signal indicating that comparison is completed. The compare result is then latched in as a data bit and the SAR advances to the next test value. Once all bits have been converted, an End-of-Conversion (EOC) is signaled. If the EOC does not occur by the end of the system clock, a metastability error is detected. The current bit that never finished comparison is forced high and all other unconverted bits are forced low.
摘要翻译： 纠正异步连续逼近寄存器（SAR）模数转换器（ADC）检测并修正亚稳态误差。 模拟信号由系统时钟同步采样，但数据位异步转换。 一个有效的检测器比较了比较采样电压与从SAR的数字测试值产生的DAC电压的比较器的真和补输出。 一旦真实和补码输出偏离了逻辑阈值，有效检测器激活一个VALID信号，指示比较完成。 然后将比较结果锁存为数据位，SAR将进入下一个测试值。 一旦所有位都被转换，就会发出转换结束（EOC）信号。 如果EOC在系统时钟结束时没有发生，则会检测到亚稳态错误。 从未完成比较的当前位被强制为高，所有其他未转换的位被强制为低电平。
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2.发明授权Digitally-programmable gain amplifier with direct-charge transfer and offset cancellation 有权具有直接电荷传输和偏移消除的数字可编程增益放大器公开(公告)号：US09190961B1
公开(公告)日：2015-11-17
申请号：US14264252
申请日：2014-04-29
CPC分类号： H03F1/0233 , H03F1/0266 , H03F3/005 , H03F3/38 , H03F3/45071 , H03F3/45475 , H03F3/45605 , H03F2200/249 , H03F2200/405 , H03F2200/411 , H03F2200/471 , H03F2203/45116 , H03F2203/45512 , H03F2203/45536 , H03F2203/45544 , H03F2203/45616 , H03G1/0094 , H03G3/001 , H03G3/002
摘要： A Programmable-Gain Amplifier (PGA) has a digital value that programmably adjusts the gain of the analog amplifier. A variable capacitor has several switched sub-capacitors that are enabled by the digital value. Enabled sub-capacitors are switched between a sampled input and a virtual ground on one terminal, and connect to a summing node on the other terminal. The summing node connects to the inverting input of an op amp either through a switch or through a double-sampling capacitor that stores an offset. A feedback capacitor is in parallel with a sampling capacitor during a second clock phase when direct-charge transfer occurs, reducing power consumption of the amplifier. The feedback capacitor samples the sampled input during the first clock phase. The PGA gain is proportional to the sum of capacitances of enabled sub-capacitors. The gain can be adjusted for sensor inputs to an Analog Front-End (AFE), such as for an electro-cardiogram (ECG).
摘要翻译： 可编程增益放大器（PGA）具有可编程调节模拟放大器增益的数字值。 可变电容器具有通过数字值使能的几个开关子电容器。 启用子电容器在一个终端上的采样输入和虚拟地之间切换，并连接到另一个终端上的求和节点。 求和节点通过开关或通过存储偏移的双采样电容连接到运算放大器的反相输入。 当直接电荷转移发生时，反馈电容器在第二个时钟相位期间与采样电容并联，从而降低放大器的功耗。 反馈电容在第一个时钟阶段对采样输入进行采样。 PGA增益与使能子电容的电容之和成正比。 可以调整模拟前端（AFE）的传感器输入的增益，例如电心电图（ECG）。
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