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公开(公告)号：US20180254750A1
公开(公告)日：2018-09-06
申请号：US15699868
申请日：2017-09-08
发明人： Junya MATSUNO , Kazuyoshi MURAOKA , Masami MASUDA , Yuui SHIMIZU , Masatoshi KOHNO , Masahiro HOSOYA
CPC分类号： H03F1/083 , H03F1/0266 , H03F1/086 , H03F1/223 , H03F1/3211 , H03F3/45076 , H03F3/45183 , H03F3/4521 , H03F3/72 , H03F2200/405 , H03F2203/45506 , H03K17/18
摘要： According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.
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公开(公告)号：US20180138881A1
公开(公告)日：2018-05-17
申请号：US15853950
申请日：2017-12-25
发明人： Hua LONG , Liyang ZHANG , Zhenjuan CHENG , Dongjie TANG , Qian ZHAO
CPC分类号： H03G3/3042 , H03F1/0211 , H03F1/0261 , H03F1/565 , H03F3/19 , H03F3/195 , H03F3/21 , H03F3/45 , H03F2200/111 , H03F2200/18 , H03F2200/36 , H03F2200/387 , H03F2200/405 , H03F2200/411 , H03F2200/451 , H03F2200/462 , H03G1/0088
摘要： A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.
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公开(公告)号：US09966920B2
公开(公告)日：2018-05-08
申请号：US15413544
申请日：2017-01-24
发明人： Chun-Hsiung Chang
CPC分类号： H03G3/3042 , H03F1/0216 , H03F3/19 , H03F3/21 , H03F2200/405 , H03F2200/451 , H03F2200/516
摘要： A power amplifier circuit includes a power supply module and serially connected multi-stages of amplifier circuit. The multi-stages of amplifier circuit, coupled to the power supply module for amplifying an radio frequency (RF) input signal as an RF output signal, which include a driver stage of circuit and a gain stage of circuit. The driver stage of circuit receives and amplifies the RF input signal. The driver stage of circuit is powered by a first supply voltage received from the power supply module. The gain stage of circuit amplifies the signal received from previous stage of amplifier circuit and outputs the RF output signal. The gain stage of circuit is powered by a second supply voltage received from the power supply module. When the power amplifier circuit is operated in a back-off region, the first supply voltage is lower than the second supply voltage.
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公开(公告)号：US20180102749A1
公开(公告)日：2018-04-12
申请号：US15725212
申请日：2017-10-04
发明人： Payam Heydari , Seyed Mohammad Hossein Mohammadnezhad , Alireza Karimi Bidhendi , Michael M. Green , David Howard , Edward Preisler
CPC分类号： H03F3/085 , H03F1/347 , H03F1/42 , H03F1/483 , H03F3/08 , H03F3/3432 , H03F3/50 , H03F2200/135 , H03F2200/405 , H03F2203/5036
摘要： Design of ultra broadband transimpedance amplifiers (TIA) for optical fiber communications is disclosed. In one embodiment, a TIA comprises a gm-boosted dual-feedback common-base stage, a level shifter and an RC-degenerated common-emitter stage, and a first emitter-follower stage, wherein the first emitter follower stage is inductively degenerated. An output of the TIA is buffered using a second emitter-follower stage.
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公开(公告)号：US20170288618A1
公开(公告)日：2017-10-05
申请号：US15087711
申请日：2016-03-31
发明人： Georgios Asmanis , Faouzi Chaahoub
CPC分类号： H03F3/08 , H03F1/34 , H03F2200/375 , H03F2200/405 , H03G3/001 , H03G3/3084 , H04B10/07955 , H04B10/6931 , H04B10/6933
摘要： A digitally-controlled transimpedance amplifier (TIA) circuit is provided in which a plurality of feedback loops are digitally controlled, including, but not limited to, the DC offset cancellation loop, the variable gain control loop, and the TIA feedback impedance adjustment loop. The digitally-controlled TIA circuit includes digital loop-control circuitry that consumes less area on the TIA IC chip than the analog circuitry traditionally used to perform the feedback loop control in the analog domain. In addition, because digital logic continues to shrink as IC processes continue to evolve, the size of the IC chip packages will further decrease over time, leading to a smaller footprint in systems in which they are employed. The digital loop control circuitry is also capable of independently varying the gains of multiple gain stages of the variable gain control circuit to provide better control over the gain stages and better overall performance of the TIA circuit.
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公开(公告)号：US09780737B1
公开(公告)日：2017-10-03
申请号：US15087711
申请日：2016-03-31
发明人： Georgios Asmanis , Faouzi Chaahoub
IPC分类号： H03F3/08 , H03F1/08 , H03F1/34 , H03G3/00 , H04B10/079
CPC分类号： H03F3/08 , H03F1/34 , H03F2200/375 , H03F2200/405 , H03G3/001 , H03G3/3084 , H04B10/07955 , H04B10/6931 , H04B10/6933
摘要： A digitally-controlled transimpedance amplifier (TIA) circuit is provided in which a plurality of feedback loops are digitally controlled, including, but not limited to, the DC offset cancellation loop, the variable gain control loop, and the TIA feedback impedance adjustment loop. The digitally-controlled TIA circuit includes digital loop-control circuitry that consumes less area on the TIA IC chip than the analog circuitry traditionally used to perform the feedback loop control in the analog domain. In addition, because digital logic continues to shrink as IC processes continue to evolve, the size of the IC chip packages will further decrease over time, leading to a smaller footprint in systems in which they are employed. The digital loop control circuitry is also capable of independently varying the gains of multiple gain stages of the variable gain control circuit to provide better control over the gain stages and better overall performance of the TIA circuit.
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公开(公告)号：US20170222610A1
公开(公告)日：2017-08-03
申请号：US15489187
申请日：2017-04-17
发明人： Vadim V. Ivanov , Vaibhav Kumar , Munaf H. Shaik
CPC分类号： H03F3/68 , H03F1/086 , H03F1/14 , H03F1/3211 , H03F1/3223 , H03F3/211 , H03F3/45183 , H03F3/45475 , H03F3/45959 , H03F3/45986 , H03F3/72 , H03F2200/135 , H03F2200/156 , H03F2200/405 , H03F2200/459 , H03F2200/78 , H03F2201/3218 , H03F2203/45026 , H03F2203/45366 , H03F2203/45424 , H03F2203/45434 , H03F2203/45528 , H03F2203/45544 , H03F2203/45548 , H03F2203/45594 , H03F2203/45614 , H03F2203/45616 , H03F2203/45636 , H03F2203/45674 , H03F2203/45724 , H03F2203/45726 , H03F2203/7206
摘要： Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions.
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公开(公告)号：US09667199B1
公开(公告)日：2017-05-30
申请号：US15178545
申请日：2016-06-09
发明人： Roy McLaren
CPC分类号： H03F1/0288 , H03F1/56 , H03F3/195 , H03F3/602 , H03F2200/387 , H03F2200/405 , H03F2200/408 , H03F2200/451 , H03F2200/541
摘要： A Doherty amplifier includes an output combining network that has a first combining network input coupled to a main amplifier path, a lowest-order combining network input coupled to a lowest-order peaking amplifier path, and N−2 additional combining network inputs coupled to other peaking amplifier paths. A final summing node is coupled to the combining network output, and is directly coupled to the first combining network input. N−2 intermediate summing nodes are coupled to the N−2 additional combining network inputs. An offset line is coupled between the lowest-order combining network input and a lowest-order summing node. A longest phase delay imparted by the output combining network on a peaking RF signal between the lowest-order combining network input and the final summing node is greater than all other phase delays imparted on any other RF signal provided to the first combining network input and the N−2 additional combining network inputs.
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公开(公告)号：US20170126191A1
公开(公告)日：2017-05-04
申请号：US14927885
申请日：2015-10-30
发明人： Chakravartula Nallani , Rahul Shringarpure , Georgios Asmanis , Faouzi Chaahoub , Kishan Venkataramu
CPC分类号： H03G3/3084 , H01L31/02016 , H03F1/083 , H03F1/22 , H03F1/32 , H03F3/08 , H03F3/45094 , H03F2200/294 , H03F2200/339 , H03F2200/405 , H03F2200/435 , H03F2200/78 , H03F2203/45374 , H03F2203/45396 , H03F2203/45562 , H03F2203/45644 , H03F2203/45702 , H03G5/28 , H04B10/40
摘要： An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier.
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10.发明申请公开(公告)号：US20170093505A1
公开(公告)日：2017-03-30
申请号：US15377755
申请日：2016-12-13
发明人： David Steven Ripley , Sabah Khesbak , Benjamin Bartram , Kevin Lee Cobley , Robert Astle Henshaw , Julian Hildersley , Robert John Thompson
CPC分类号： H04B17/13 , H03F1/0211 , H03F1/0216 , H03F1/0222 , H03F1/0227 , H03F1/025 , H03F1/30 , H03F1/301 , H03F1/32 , H03F1/56 , H03F3/19 , H03F3/193 , H03F3/21 , H03F3/211 , H03F3/245 , H03F3/68 , H03F3/72 , H03F2200/102 , H03F2200/108 , H03F2200/111 , H03F2200/15 , H03F2200/387 , H03F2200/405 , H03F2200/429 , H03F2200/451 , H03F2200/462 , H03F2200/465 , H03F2200/471 , H03F2200/507 , H03F2200/511 , H03F2203/21106 , H03G3/30 , H03G3/3036 , H03G3/3042 , H04B1/40 , H04W88/02
摘要： Methods of calibrating a power amplifier system to compensate for envelope amplitude misalignment are provided. In certain configurations, a method of calibrating a power amplifier system includes amplifying a radio frequency signal from a transceiver using a power amplifier and generating a supply voltage of the power amplifier using an envelope tracker, including generating a scaled envelope signal based on a power control level signal and an envelope signal, and shaping the scaled envelope signal using a shaping table generated at a target gain compression. The method further includes changing a scaling of the scaled envelope signal using a calibration module, monitoring an output of the power amplifier to determine an amount of scaling of the scaled envelope signal at which a detected gain compression of the power amplifier corresponds to the target gain compression of the shaping table, and calibrating the power amplifier system based on the determination.
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