公开(公告)号：US20100271862A1

公开(公告)日：2010-10-28

申请号：US12765411

申请日：2010-04-22

申请人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

发明人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a word line decoder and local word lines, and local bit line selection units connected to each memory block connect global bit lines connected to a sense amplifier and local bit lines. Each memory block includes local word lines which extend in a first direction and are stacked in a second direction perpendicular to the first direction on a second plane perpendicular to a first plane. Local bit lines extend in the second direction to cross local word lines. Memory cells are formed at cross-points where local word lines and local bit lines cross one another.

摘要翻译： 非易失性存储器件包括三维结构中的电阻式存储器件。 块选择电路产生用于选择存储块的块选择信号。 响应于块选择信号，连接到每个存储器块的局部字线选择单元连接连接到字线解码器和本地字线的全局字线，并且连接到每个存储器块的局部位线选择单元将连接到 一个读出放大器和本地位线。 每个存储块包括在垂直于第一平面的第二平面上沿第一方向延伸并且沿垂直于第一方向的第二方向堆叠的局部字线。 局部位线在第二个方向上延伸以跨越局部字线。 存储单元在本地字线和局部位线交叉的交点处形成。

公开(公告)号：US08331152B2

公开(公告)日：2012-12-11

申请号：US12765411

申请日：2010-04-22

申请人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

发明人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a word line decoder and local word lines, and local bit line selection units connected to each memory block connect global bit lines connected to a sense amplifier and local bit lines. Each memory block includes local word lines which extend in a first direction and are stacked in a second direction perpendicular to the first direction on a second plane perpendicular to a first plane. Local bit lines extend in the second direction to cross local word lines. Memory cells are formed at cross-points where local word lines and local bit lines cross one another.

摘要翻译： 非易失性存储器件包括三维结构中的电阻式存储器件。 块选择电路产生用于选择存储块的块选择信号。 响应于块选择信号，连接到每个存储器块的局部字线选择单元连接连接到字线解码器和本地字线的全局字线，并且连接到每个存储器块的局部位线选择单元将连接到 一个读出放大器和本地位线。 每个存储块包括在垂直于第一平面的第二平面上沿第一方向延伸并且沿垂直于第一方向的第二方向堆叠的局部字线。 局部位线在第二个方向上延伸以跨越局部字线。 存储单元在本地字线和局部位线交叉的交点处形成。

公开(公告)号：US20110012081A1

公开(公告)日：2011-01-20

申请号：US12822302

申请日：2010-06-24

申请人： HongSik YOON ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  MInyoung Park

发明人： HongSik YOON ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  MInyoung Park

IPC分类号： H01L45/00 ,  H01L29/82

CPC分类号： H01L21/8229 ,  H01L27/224 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/145

摘要： A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.

摘要翻译： 半导体存储器件包括第一导线，与第一导线交叉的第二导线，设置在第二导线与第一导线相交并与第一导线相连的位置处的电阻变化部，以及 所述第二导线和设置在所述电阻变化部和所述第二导线之间的机械开关。 机械开关包括纳米管。

公开(公告)号：US08581346B2

公开(公告)日：2013-11-12

申请号：US12822302

申请日：2010-06-24

申请人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

发明人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

IPC分类号： H01L21/8229 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L21/8229 ,  H01L27/224 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/145

摘要： A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.

摘要翻译： 半导体存储器件包括第一导线，与第一导线交叉的第二导线，设置在第二导线与第一导线相交并与第一导线相连的位置处的电阻变化部，以及 所述第二导线和设置在所述电阻变化部和所述第二导线之间的机械开关。 机械开关包括纳米管。

公开(公告)号：US08338224B2

公开(公告)日：2012-12-25

申请号：US12621007

申请日：2009-11-18

申请人： HongSik Yoon ,  Ingyu Baek ,  Hyunjun Sim ,  Jin-Shi Zhao ,  Minyoung Park

发明人： HongSik Yoon ,  Ingyu Baek ,  Hyunjun Sim ,  Jin-Shi Zhao ,  Minyoung Park

IPC分类号： H01L21/06

CPC分类号： H01L27/2409 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： Provided is a resistance random access memory device and a method of fabricating, the same. The method includes forming a bit-line stack in which a plurality of local bit-lines are vertically stacked on a substrate, forming a word-line including a plurality of local word-lines that extend in a vertical direction toward a side of the bit-line stack and a connection line that extends in a horizontal direction to connect the plurality of local word-lines with one another, and forming a resistance memory thin film between the bit-line stack and the word-line. The present inventive concept can realize a highly dense memory array with 3D cross-point architecture by simplified processes.

摘要翻译： 提供一种电阻随机存取存储器件及其制造方法。 该方法包括形成位线堆叠，其中多个局部位线垂直堆叠在基板上，形成包括在垂直方向上朝向该位的一侧延伸的多个局部字线的字线 线堆叠和连接线，其在水平方向上延伸以将多个本地字线彼此连接，并且在位线堆叠和字线之间形成电阻存储器薄膜。 本发明的概念可以通过简化的过程实现具有3D交叉点架构的高密度存储器阵列。

公开(公告)号：US20100178729A1

公开(公告)日：2010-07-15

申请号：US12621007

申请日：2009-11-18

申请人： HongSik Yoon ,  Ingyu Baek ,  Hyunjun Sim ,  Jin-Shi Zhao ,  Minyoung Park

发明人： HongSik Yoon ,  Ingyu Baek ,  Hyunjun Sim ,  Jin-Shi Zhao ,  Minyoung Park

IPC分类号： H01L21/16

CPC分类号： H01L27/2409 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： Provided is a resistance random access memory device and a method of fabricating, the same. The method includes forming a bit-line stack in which a plurality of local bit-lines are vertically stacked on a substrate, forming a word-line including a plurality of local word-lines that extend in a vertical direction toward a side of the bit-line stack and a connection line that extends in a horizontal direction to connect the plurality of local word-lines with one another, and forming a resistance memory thin film between the bit-line stack and the word-line. The present inventive concept can realize a highly dense memory array with 3D cross-point architecture by simplified processes.

摘要翻译： 提供一种电阻随机存取存储器件及其制造方法。 该方法包括形成位线堆叠，其中多个局部位线垂直堆叠在基板上，形成包括在垂直方向上朝向该位的一侧延伸的多个局部字线的字线 线堆叠和连接线，其在水平方向上延伸以将多个本地字线彼此连接，并且在位线堆叠和字线之间形成电阻存储器薄膜。 本发明的概念可以通过简化的过程实现具有3D交叉点架构的高密度存储器阵列。

公开(公告)号：US07772067B2

公开(公告)日：2010-08-10

申请号：US12039370

申请日：2008-02-28

申请人： Jinil Lee ,  Suk Ho Joo ,  Dohyung Kim ,  Hyunjun Sim ,  Hyeyoung Park ,  Sunglae Cho ,  Dong-Hyun Im

发明人： Jinil Lee ,  Suk Ho Joo ,  Dohyung Kim ,  Hyunjun Sim ,  Hyeyoung Park ,  Sunglae Cho ,  Dong-Hyun Im

IPC分类号： H01L21/336

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1616 ,  H01L45/1683

摘要： Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.

摘要翻译： 形成相变存储器件的方法包括抑制相变材料中的空隙形成的技术，以增加器件的可靠性。 抑制空隙形成的这些技术使用电绝缘的生长抑制层来引导存储单元（例如，PRAM单元）内的相变材料区域的形成。 特别地，形成集成电路存储器件的方法包括在衬底上形成其中具有开口的层间绝缘层，然后用支撑生长的种子层（即生长增强层）来衬套开口的侧壁 相变材料。 然后在围绕开口的层间绝缘层的一部分上选择性地形成电绝缘的生长抑制层。 生长抑制层的形成之后是选择性地生长开口中的相变材料区域，而不是在生长抑制层上生长的步骤。

公开(公告)号：US20090130797A1

公开(公告)日：2009-05-21

申请号：US12039370

申请日：2008-02-28

申请人： Jinil Lee ,  Suk Ho Joo ,  Dohyung Kim ,  Hyunjun Sim ,  Hyeyoung Park ,  Sunglae Cho ,  Dong-Hyun Im

发明人： Jinil Lee ,  Suk Ho Joo ,  Dohyung Kim ,  Hyunjun Sim ,  Hyeyoung Park ,  Sunglae Cho ,  Dong-Hyun Im

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1616 ,  H01L45/1683

摘要： Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.

摘要翻译： 形成相变存储器件的方法包括抑制相变材料中的空隙形成的技术，以增加器件的可靠性。 抑制空隙形成的这些技术使用电绝缘的生长抑制层来引导存储单元（例如，PRAM单元）内的相变材料区域的形成。 特别地，形成集成电路存储器件的方法包括在衬底上形成其中具有开口的层间绝缘层，然后用支撑生长的种子层（即生长增强层）来衬套开口的侧壁 相变材料。 然后在围绕开口的层间绝缘层的一部分上选择性地形成电绝缘的生长抑制层。 生长抑制层的形成之后是选择性地生长开口中的相变材料区域，而不是在生长抑制层上生长的步骤。