公开(公告)号：US08338224B2

公开(公告)日：2012-12-25

申请号：US12621007

申请日：2009-11-18

申请人： HongSik Yoon ,  Ingyu Baek ,  Hyunjun Sim ,  Jin-Shi Zhao ,  Minyoung Park

发明人： HongSik Yoon ,  Ingyu Baek ,  Hyunjun Sim ,  Jin-Shi Zhao ,  Minyoung Park

IPC分类号： H01L21/06

CPC分类号： H01L27/2409 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： Provided is a resistance random access memory device and a method of fabricating, the same. The method includes forming a bit-line stack in which a plurality of local bit-lines are vertically stacked on a substrate, forming a word-line including a plurality of local word-lines that extend in a vertical direction toward a side of the bit-line stack and a connection line that extends in a horizontal direction to connect the plurality of local word-lines with one another, and forming a resistance memory thin film between the bit-line stack and the word-line. The present inventive concept can realize a highly dense memory array with 3D cross-point architecture by simplified processes.

摘要翻译： 提供一种电阻随机存取存储器件及其制造方法。 该方法包括形成位线堆叠，其中多个局部位线垂直堆叠在基板上，形成包括在垂直方向上朝向该位的一侧延伸的多个局部字线的字线 线堆叠和连接线，其在水平方向上延伸以将多个本地字线彼此连接，并且在位线堆叠和字线之间形成电阻存储器薄膜。 本发明的概念可以通过简化的过程实现具有3D交叉点架构的高密度存储器阵列。

公开(公告)号：US20100178729A1

公开(公告)日：2010-07-15

申请号：US12621007

申请日：2009-11-18

申请人： HongSik Yoon ,  Ingyu Baek ,  Hyunjun Sim ,  Jin-Shi Zhao ,  Minyoung Park

发明人： HongSik Yoon ,  Ingyu Baek ,  Hyunjun Sim ,  Jin-Shi Zhao ,  Minyoung Park

IPC分类号： H01L21/16

CPC分类号： H01L27/2409 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： Provided is a resistance random access memory device and a method of fabricating, the same. The method includes forming a bit-line stack in which a plurality of local bit-lines are vertically stacked on a substrate, forming a word-line including a plurality of local word-lines that extend in a vertical direction toward a side of the bit-line stack and a connection line that extends in a horizontal direction to connect the plurality of local word-lines with one another, and forming a resistance memory thin film between the bit-line stack and the word-line. The present inventive concept can realize a highly dense memory array with 3D cross-point architecture by simplified processes.

摘要翻译： 提供一种电阻随机存取存储器件及其制造方法。 该方法包括形成位线堆叠，其中多个局部位线垂直堆叠在基板上，形成包括在垂直方向上朝向该位的一侧延伸的多个局部字线的字线 线堆叠和连接线，其在水平方向上延伸以将多个本地字线彼此连接，并且在位线堆叠和字线之间形成电阻存储器薄膜。 本发明的概念可以通过简化的过程实现具有3D交叉点架构的高密度存储器阵列。

公开(公告)号：US20100271862A1

公开(公告)日：2010-10-28

申请号：US12765411

申请日：2010-04-22

申请人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

发明人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a word line decoder and local word lines, and local bit line selection units connected to each memory block connect global bit lines connected to a sense amplifier and local bit lines. Each memory block includes local word lines which extend in a first direction and are stacked in a second direction perpendicular to the first direction on a second plane perpendicular to a first plane. Local bit lines extend in the second direction to cross local word lines. Memory cells are formed at cross-points where local word lines and local bit lines cross one another.

摘要翻译： 非易失性存储器件包括三维结构中的电阻式存储器件。 块选择电路产生用于选择存储块的块选择信号。 响应于块选择信号，连接到每个存储器块的局部字线选择单元连接连接到字线解码器和本地字线的全局字线，并且连接到每个存储器块的局部位线选择单元将连接到 一个读出放大器和本地位线。 每个存储块包括在垂直于第一平面的第二平面上沿第一方向延伸并且沿垂直于第一方向的第二方向堆叠的局部字线。 局部位线在第二个方向上延伸以跨越局部字线。 存储单元在本地字线和局部位线交叉的交点处形成。

公开(公告)号：US08581346B2

公开(公告)日：2013-11-12

申请号：US12822302

申请日：2010-06-24

申请人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

发明人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

IPC分类号： H01L21/8229 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L21/8229 ,  H01L27/224 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/145

摘要： A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.

摘要翻译： 半导体存储器件包括第一导线，与第一导线交叉的第二导线，设置在第二导线与第一导线相交并与第一导线相连的位置处的电阻变化部，以及 所述第二导线和设置在所述电阻变化部和所述第二导线之间的机械开关。 机械开关包括纳米管。

公开(公告)号：US08331152B2

公开(公告)日：2012-12-11

申请号：US12765411

申请日：2010-04-22

申请人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

发明人： HongSik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  Minyoung Park

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a word line decoder and local word lines, and local bit line selection units connected to each memory block connect global bit lines connected to a sense amplifier and local bit lines. Each memory block includes local word lines which extend in a first direction and are stacked in a second direction perpendicular to the first direction on a second plane perpendicular to a first plane. Local bit lines extend in the second direction to cross local word lines. Memory cells are formed at cross-points where local word lines and local bit lines cross one another.

摘要翻译： 非易失性存储器件包括三维结构中的电阻式存储器件。 块选择电路产生用于选择存储块的块选择信号。 响应于块选择信号，连接到每个存储器块的局部字线选择单元连接连接到字线解码器和本地字线的全局字线，并且连接到每个存储器块的局部位线选择单元将连接到 一个读出放大器和本地位线。 每个存储块包括在垂直于第一平面的第二平面上沿第一方向延伸并且沿垂直于第一方向的第二方向堆叠的局部字线。 局部位线在第二个方向上延伸以跨越局部字线。 存储单元在本地字线和局部位线交叉的交点处形成。

公开(公告)号：US20110012081A1

公开(公告)日：2011-01-20

申请号：US12822302

申请日：2010-06-24

申请人： HongSik YOON ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  MInyoung Park

发明人： HongSik YOON ,  Jinshi Zhao ,  Ingyu Baek ,  Hyunjun Sim ,  MInyoung Park

IPC分类号： H01L45/00 ,  H01L29/82

CPC分类号： H01L21/8229 ,  H01L27/224 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/145

摘要： A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.

摘要翻译： 半导体存储器件包括第一导线，与第一导线交叉的第二导线，设置在第二导线与第一导线相交并与第一导线相连的位置处的电阻变化部，以及 所述第二导线和设置在所述电阻变化部和所述第二导线之间的机械开关。 机械开关包括纳米管。

公开(公告)号：US08264018B2

公开(公告)日：2012-09-11

申请号：US12777683

申请日：2010-05-11

申请人： Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

发明人： Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

IPC分类号： H01L29/80

CPC分类号： H01L27/228 ,  H01L27/0207 ,  H01L27/2454 ,  H01L27/249

摘要： Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.

摘要翻译： 提供了一种半导体存储器件。 半导体存储器件可以包括在基本上垂直于半导体衬底的上表面的方向上延伸的局部位线和与局部位线相交的局部字线。 局部位线电连接到贯穿位线晶体管的栅极的位线通道柱，并且本地字线电连接到贯穿字线晶体管的栅极的字线通道柱。

公开(公告)号：US20120306004A1

公开(公告)日：2012-12-06

申请号：US13585119

申请日：2012-08-14

申请人： Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

发明人： Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

IPC分类号： H01L29/78

CPC分类号： H01L27/228 ,  H01L27/0207 ,  H01L27/2454 ,  H01L27/249

摘要： Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.

摘要翻译： 提供了一种半导体存储器件。 半导体存储器件可以包括在基本上垂直于半导体衬底的上表面的方向上延伸的局部位线和与局部位线相交的局部字线。 局部位线电连接到贯穿位线晶体管的栅极的位线通道柱，并且本地字线电连接到贯穿字线晶体管的栅极的字线通道柱。

公开(公告)号：US20100289084A1

公开(公告)日：2010-11-18

申请号：US12777683

申请日：2010-05-11

申请人： Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

发明人： Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

IPC分类号： H01L29/78

CPC分类号： H01L27/228 ,  H01L27/0207 ,  H01L27/2454 ,  H01L27/249

摘要： Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.

摘要翻译： 提供了一种半导体存储器件。 半导体存储器件可以包括在基本上垂直于半导体衬底的上表面的方向上延伸的局部位线和与局部位线相交的局部字线。 局部位线电连接到贯穿位线晶体管的栅极的位线通道柱，并且本地字线电连接到贯穿字线晶体管的栅极的字线通道柱。

公开(公告)号：US08824184B2

公开(公告)日：2014-09-02

申请号：US13587476

申请日：2012-08-16

申请人： Ingyu Baek ,  Chanjin Park ,  Hyunsu Ju

发明人： Ingyu Baek ,  Chanjin Park ,  Hyunsu Ju

IPC分类号： G11C5/02 ,  G11C8/14 ,  G11C7/18 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C8/14 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147

摘要： A semiconductor memory device includes a stacked structure including a plurality of wordline structures sequentially stacked that each include: a plurality of wordlines with sidewalls and extending in a first direction on the substrate, and a connecting pad extending in a second direction on the substrate and being connected in common to the plurality of wordlines. A plurality of interconnections at a height over the substrate are connected to the connecting pads of the wordline structures, respectively. The device further includes bitlines substantially vertical to a top surface of the substrate and crossing one of the sidewalls of the plurality of wordlines, and memory elements between the bitlines and the plurality of wordlines, respectively. A length of the connecting pad in the second direction is substantially equal to a product of a minimum pitch between the interconnections and a stack number of one of the plurality of wordlines.

摘要翻译： 半导体存储器件包括堆叠结构，其包括顺序层叠的多个字线结构，每个字线包括：具有侧壁并在衬底上沿第一方向延伸的多个字线，以及在衬底上沿第二方向延伸的连接焊盘， 与多个字线共同连接。 在衬底上的高度处的多个互连分别连接到字线结构的连接焊盘。 该装置还包括基本上垂直于衬底的顶表面并且跨越多个字线的侧壁中的一个以及位线和多个字线之间的存储元件的位线。 连接焊盘在第二方向上的长度基本上等于互连之间的最小间距和多个字线之一的堆叠数的乘积。