公开(公告)号：US4090255A

公开(公告)日：1978-05-16

申请号：US662309

申请日：1976-03-01

申请人： Horst H. Berger ,  Klaus Heuber ,  Wilfried Klein ,  Knut Najmann ,  Siegfried Wiedmann

发明人： Horst H. Berger ,  Klaus Heuber ,  Wilfried Klein ,  Knut Najmann ,  Siegfried Wiedmann

IPC分类号： G11C11/414 ,  G11C11/411 ,  G11C11/416 ,  G11C11/40 ,  G11C7/00

CPC分类号： G11C11/416 ,  G11C11/4113

摘要： The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases.This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits.This permits high speed, low operating current, large scale memory systems to be built.

摘要翻译： 本发明涉及用于操作集成半导体存储器存储系统的读/写周期的电路装置，其存储单元由具有双极性开关晶体管的触发器组成，肖特基二极管作为将单元耦合到位线的读/写元件和高 电阻电阻或作为电流源控制的晶体管作为负载元件，分几个阶段。

公开(公告)号：US4158783A

公开(公告)日：1979-06-19

申请号：US823314

申请日：1977-08-10

申请人： Horst H. Berger ,  Siegfried Wiedmann

发明人： Horst H. Berger ,  Siegfried Wiedmann

IPC分类号： H01L21/8222 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L27/04 ,  H03K19/08

CPC分类号： H01L27/0821 ,  H01L27/0233 ,  Y10S148/038 ,  Y10S148/106 ,  Y10S148/167

摘要： Improved integrated bipolar semiconductor structures and a method of fabricating same are disclosed. The logic circuit structures disclosed have enhanced density and speed power product. The teaching of the disclosed logic circuit structures includes utilization and extension of the known concepts of Current Hogging Injection Logic (CHIL) and Integrated Injection Logic (I.sup.2 L). The disclosed method of fabrication includes a minimum number of process steps, where each step is well within the state of the art and does not contain critical alignment problems.

摘要翻译： 公开了改进的集成双极半导体结构及其制造方法。 所公开的逻辑电路结构具有增强的密度和速度功率产品。 所公开的逻辑电路结构的教导包括利用和扩展电流陷波注入逻辑（CHIL）和集成注入逻辑（I2L）的已知概念。 所公开的制造方法包括最少数量的工艺步骤，其中每个步骤都处于现有技术状态，并且不包含关键对准问题。

公开(公告)号：US5477489A

公开(公告)日：1995-12-19

申请号：US407505

申请日：1995-03-20

申请人： Siegfried Wiedmann

发明人： Siegfried Wiedmann

IPC分类号： G11C8/16 ,  G11C7/00

CPC分类号： G11C8/16

摘要： A memory cell has the read current from the bit lines isolated from the bistable storage latch in the cell. Internal nodes of the bistable storage latch control isolated gates of MOS read transistors which gate the read current from the bit lines to a local node within the memory cell. The read current is then switched to ground from the local node by a read switch transistor. The read switch transistor is gated by the read row line. The read current is isolated from the read row line because the read row line is only connected to the isolated gate of the read switch transistor. The read current is also isolated from the bistable storage latch since the read transistors are connected at their isolated MOS gates to the bistable's nodes. This isolation of the read current allows additional read ports to be added without disrupting the cell's stability or write performance. The read ports are optimized independently of the bistable stability and write performance and even optimized independently of other read ports. For allowing better control of the read currents, a current-mirroring row driver causes the current in the row driver to be mirrored by the read currents flowing through the read switch transistors.

摘要翻译： 存储器单元具有从单元中的双稳​​态存储器锁存器隔开的位线的读取电流。 双稳态存储锁存器的内部节点控制MOS读取晶体管的隔离栅极，其将读取的电流从位线切换到存储器单元内的本地节点。 然后，读取电流通过读开关晶体管从本地节点切换到地。 读取开关晶体管由读取行线选通。 读取电流与读取行线隔离，因为读取行线仅连接到读取开关晶体管的隔离栅极。 读取电流也与双稳态存储锁存器隔离，因为读取晶体管在其隔离MOS栅极连接到双稳态节点。 读取电流的这种隔离允许添加额外的读取端口，而不会中断单元的稳定性或写入性能。 读取端口独立于双稳态稳定性和写入性能进行优化，甚至独立于其他读端口进行优化。 为了更好地控制读取电流，电流镜像行驱动器使得行驱动器中的电流被流过读开关晶体管的读电流镜像。

公开(公告)号：US5453949A

公开(公告)日：1995-09-26

申请号：US298593

申请日：1994-08-31

申请人： Siegfried Wiedmann ,  Frederick Buckley, III

发明人： Siegfried Wiedmann ,  Frederick Buckley, III

IPC分类号： G11C11/412 ,  G11C11/418 ,  G11C11/40

CPC分类号： G11C11/418 ,  G11C11/412

摘要： A static RAM memory is ideally suited for BiCMOS processes. As in standard CMOS memory cells, the cells have cross-coupled inverters that have more efficient n-channel transistors for the drive transistors, which pull a bit line low during a read operation. The weaker p-channel transistors are used for load transistors in the cross-coupled inverters, adding to cell stability while requiring no power. In contrast to prior-art cells, p-channel pass transistors are used. Common-emitter word-line drivers are also used that require a small input-voltage swing in comparison with the large word-line voltage swing. A low voltage on the word line selects a memory cell by causing p-channel pass transistors to conduct, coupling bit lines to the cross-coupled inverters in the memory cell. Power consumption is reduced since only one selected word line is at a low voltage, while the deselected word lines are at a high voltage. Common-emitter word-line drivers have a conduction path from the positive supply terminal to ground when the output word line is low, but no conduction path when the output word line is high. Thus only the common-emitter word-line driver that is connected to the selected low word line consumes appreciable power.

摘要翻译： 静态RAM存储器非常适合BiCMOS工艺。 与标准CMOS存储单元一样，这些单元具有交叉耦合的反相器，其具有用于驱动晶体管的更有效的n沟道晶体管，其在读取操作期间将位线拉低。 较弱的p沟道晶体管用于交叉耦合的逆变器中的负载晶体管，增加了电池的稳定性，同时不需要电源。 与现有技术的单元相反，使用p沟道传输晶体管。 与大字线电压摆幅相比，也使用共发射极字线驱动器，需要较小的输入电压摆幅。 字线上的低电压通过使p沟道传输晶体管导通，将位线耦合到存储单元中的交叉耦合的反相器来选择存储单元。 由于只有一个选定的字线处于低电压，而取消选择的字线处于高电压，所以功耗降低。 当输出字线为低电平时，共发射极字线驱动器具有从正电源端子接地的导通路径，而当输出字线为高电平时，则不具有导通路径。 因此，只有连接到所选低字线的共发射极字线驱动器消耗明显的功率。