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公开(公告)号：US4090255A
公开(公告)日：1978-05-16
申请号：US662309
申请日：1976-03-01
IPC分类号： G11C11/414 , G11C11/411 , G11C11/416 , G11C11/40 , G11C7/00
CPC分类号： G11C11/416 , G11C11/4113
摘要： The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases.This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits.This permits high speed, low operating current, large scale memory systems to be built.
摘要翻译： 本发明涉及用于操作集成半导体存储器存储系统的读/写周期的电路装置，其存储单元由具有双极性开关晶体管的触发器组成，肖特基二极管作为将单元耦合到位线的读/写元件和高 电阻电阻或作为电流源控制的晶体管作为负载元件，分几个阶段。
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公开(公告)号：US4122548A
公开(公告)日：1978-10-24
申请号：US840457
申请日：1977-10-07
IPC分类号： G11C11/41 , G11C7/04 , G11C11/411 , G11C11/414 , G11C11/416 , G11C11/40
CPC分类号： G11C11/416 , G11C11/4113
摘要： A memory storage system which utilizes semiconductor storage cells comprised of cross-coupled bipolar transistors arranged in a memory system array with an error reference circuit and a standby reference circuit that is controlled by a clock signal. The standby reference circuit and the error reference circuit are both coupled to the bit lines and selectively control a restore circuit that maintains, in the standby state, a selected potential on the bit lines such that short access times are realized and current is prevented from flowing into unselected cells when adjacent defective cells are being read or written.
摘要翻译： 一种存储器存储系统，其利用布置在存储器系统阵列中的交叉耦合双极晶体管构成的半导体存储单元，其具有由时钟信号控制的误差参考电路和备用参考电路。 待机参考电路和误差参考电路都耦合到位线，并选择性地控制恢复电路，其在待机状态下保持位线上的选定电位，使得实现短访问时间并防止电流流动 当读取或写入相邻的有缺陷的单元时，进入未选择的单元格。
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公开(公告)号：US4070656A
公开(公告)日：1978-01-24
申请号：US739669
申请日：1976-11-08
IPC分类号： G11C11/41 , G11C11/411 , G11C11/414 , G11C11/415 , G11C11/40 , G11C7/00
CPC分类号： G11C11/4113 , G11C11/415
摘要： An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.
摘要翻译： 公开了一种改进的操作单片存储器的方法以及用于实践所述改进方法的新颖且有效的电路。 在双极晶体管存储器或单片存储器中，根据本发明，在待机模式下，非常低的电流（第一级）从负载元件流向内部单元节点。 在读周期的初始部分，除了待机电流（第二电平）之外，电流也从位线流向单元节点。 在读周期或写周期的恢复周期中，短暂的脉冲被添加到备用电流（第三级），从而减少恢复时间。 本发明的实践提供了具有最小功率要求和大大减少的循环时间的单片存储器。
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4.发明授权Method and circuit arrangement for operating a highly integrated monolithic information store 失效用于操作高度集成的单片信息存储的方法和电路装置
公开(公告)号：US4007451A
公开(公告)日：1977-02-08
申请号：US633733
申请日：1975-11-20
IPC分类号： G11C11/41 , G11C11/413 , G11C11/415 , H03K19/088 , H03M7/00 , G11C11/23 , G11C7/00
CPC分类号： G11C11/415 , H03K19/088 , H03M7/005
摘要： A method and circuit arrangement for operating an information store, in particular a monolithic information store, whose storage cells and address circuits comprise bipolar transistors which are not continuously subjected to full power. The monolithic information store is readily fabricated by known planar process technology, has increased density, has reduced read/write times, reduced cycle time, and reduced power dissipation.
摘要翻译： 一种用于操作信息存储器，特别是单片信息存储器的方法和电路装置，其存储单元和地址电路包括不连续经受全功率的双极晶体管。 单片信息存储器通过已知的平面处理技术容易地制造，密度增加，读/写时间缩短，循环时间缩短，功耗降低。
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公开(公告)号：US4027176A
公开(公告)日：1977-05-31
申请号：US635539
申请日：1975-11-26
CPC分类号： H03K3/287 , G11C11/34 , G11C11/416 , H03K5/02
摘要： This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.
摘要翻译： 这教导了用于集成存储器存储系统的感测电路，其中存储单元输出由差分放大器检测，控制用作锁存器的触发器，其具有也用作锁存器的负载元件的负载元件，以确保 最佳功率和速度产品。 闩锁可以通过电流开关耦合到输出驱动器电路，电流开关与闩锁共享公共元件，以确保即使当与具有不对称控制的输出驱动器一起使用时，闩锁保持对称。
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公开(公告)号：US4023148A
公开(公告)日：1977-05-10
申请号：US635538
申请日：1975-11-26
IPC分类号： G11C11/414 , G11C11/411 , G11C11/415 , G11C11/40
CPC分类号： G11C11/415 , G11C11/4113
摘要： Modern bipolar cross coupled memory cells for high density arrays use diodes as coupling elements from the cell to the bit lines. The write operation of these cells requires a high amount of current if the current gain of the cell transistors is high. The time required to perform a write operation is prolonged significantly due to the inherent capacitors in the cell known as the Miller effect. The described circuit completely eliminates the Miller effect during the write operation and makes the required write current completely independent of the current gain of the cell transistors.In the present invention this is accomplished by dropping the word line of such a cell from a stand-by potential to a select potential, so that the inner cell nodes are equally discharged, without disturbing the state of the cell, after which the word line is pulsed up to an intermediate potential between the select potential and the stand-by potential.
摘要翻译： 用于高密度阵列的现代双极交叉耦合存储单元使用二极管作为从单元到位线的耦合元件。 如果单元晶体管的电流增益高，则这些单元的写操作需要大量的电流。 由于称为米勒效应的电池中的固有电容器，执行写入操作所需的时间显着延长。 所描述的电路在写入操作期间完全消除了米勒效应，并使所需的写入电流完全独立于单元晶体管的电流增益。
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公开(公告)号：US4542309A
公开(公告)日：1985-09-17
申请号：US468447
申请日：1983-02-22
申请人： Wilfried Klein , Erich Klink , Knut Najmann , Friedrich Wernicke
发明人： Wilfried Klein , Erich Klink , Knut Najmann , Friedrich Wernicke
CPC分类号： H03K3/287
摘要： Disclosed is a phase splitter with integrated latch circuit, where the complementary output signals generated after an input signal applied to a true-complement generator are available directly without any load by the latch circuit, where upon a premature change of the input signal there is no undesired change of the previously set switching state or of the output signals, respectively, and where a simple clocking for functional control can be used. The advantages presented by the disclosed Phase splitter substantially consist in that the speed with which the complementary output signals are supplied is extremely high since the output signals are available directly, i.e. with only one stage delay, the latch circuit being non-conductive in the stationary state, and thus in a latching process does not have to be switched from one stage to the other, but only switched on.
摘要翻译： 公开了一种具有集成锁存电路的分相器，其中在输入信号施加到真互补发生器之后产生的互补输出信号可直接获得，而锁存电路不需要任何负载，其中当输入信号的过早变化 分别预先设定的开关状态或输出信号的不期望的变化，以及可以使用用于功能控制的简单时钟。 所公开的相位分离器所呈现的优点基本上在于，互补输出信号的供给速度非常高，因为输出信号可以直接获得，即只有一级延迟，锁存电路在静态中是不导通的 状态，因此在锁定过程中不必从一个阶段切换到另一个阶段，而是仅被接通。
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公开(公告)号：US4313179A
公开(公告)日：1982-01-26
申请号：US133383
申请日：1980-03-24
IPC分类号： G11C11/41 , G11C7/02 , G11C7/06 , G11C7/20 , G11C11/4091 , G11C11/416 , G11C7/00
CPC分类号： G11C7/062 , G11C11/4091 , G11C11/416 , G11C7/065 , G11C7/20
摘要： An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch.For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0".The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.
摘要翻译： 具有存储单元的集成半导体存储器，其具有（或被设计为具有）用于其可分辨存储器状态的固有不对称访问时间。 存储器在更短的访问时间的基础上运行。 这通过利用相对不对称的感测系统来实现，优选地以预设的感测锁存器的形式。 例如，在具有比读取“1”状态的访问时间短的读取“0”状态的数字存储器的情况下，在读操作开始时，将感测锁存器设置为（较慢 ）“1”状态。 因此，只有在读取“0”的情况下，锁存器的状态变为“0”状态。 因此，实际的访问时间不再由更长的访问时间，即读取“1”确定。 访问时间由更短的访问时间确定，即读取“0”。 如果感测锁存器具有不对称访问时间，则也可以使用该概念。 那么有意的是选择相应的非对称存储单元设计。
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9.发明授权High pressure magnetron cathode assembly and sputtering apparatus utilizing same 失效高压磁控管阴极组件及利用其的溅射装置
公开(公告)号：US6110336A
公开(公告)日：2000-08-29
申请号：US131488
申请日：1998-08-10
CPC分类号： H01J37/3447 , H01J37/3405
摘要： A magnetron cathode and sputtering system in which the cathode assembly includes a diaphragm arrangement with one or more diaphragms which overlie at least the edge of the cathode at the dark side region of the gas discharge so that plasmas cannot form between the diaphragm and target. An improved sputtering is thereby obtained in a high pressure mode of operation.
摘要翻译： 一种磁控管阴极和溅射系统，其中阴极组件包括具有一个或多个隔膜的隔膜装置，其在气体放电的暗侧区域至少覆盖阴极的边缘，使得等离子体不能在隔膜和靶之间形成。 由此在高压操作模式下获得改进的溅射。
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公开(公告)号：US4552221A
公开(公告)日：1985-11-12
申请号：US517544
申请日：1983-07-27
申请人： Wilfried Klein
发明人： Wilfried Klein
CPC分类号： F16K17/042 , A62C35/64 , A62C35/68 , Y10T137/7734
摘要： In an alarm valve for permanently installed fire-extinguishing systems, having a blocking element mounted in a valve housing with an inlet and outlet and which tightly blocks the open cross-section of the housing and locking and release mechanism integrated into the valve, the improvement wherein the locking and release mechanism comprises at least one radial depression at the open cross-section of the valve mounting, at least one locking element engageable with the at least one depression to lock the blocking element in a blocking position. The locking element is maintained in the engaged position against the pressure of an extinguishing fluid in response to the pressure of a gas or mixture of gases exceeding a predetermined level which is weaker than the pressure of the extinguishing fluid.
摘要翻译： 在用于永久安装的灭火系统的报警阀中，具有安装在具有入口和出口的阀壳体中的阻塞元件并且紧密地阻塞壳体的敞开的横截面以及集成到阀中的锁定和释放机构，改进 其中所述锁定和释放机构包括在所述阀安装件的敞开横截面处的至少一个径向凹部，所述至少一个锁定元件可与所述至少一个凹部接合以将所述阻挡元件锁定在阻挡位置。 响应于超过比灭火流体的压力弱的预定水平的气体或气体混合物的压力，锁定元件抵抗灭火流体的压力保持在接合位置。
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