公开(公告)号：US08060784B1

公开(公告)日：2011-11-15

申请号：US12630163

申请日：2009-12-03

申请人： Roger Spinti ,  Howard Tang ,  San-Ta Kow ,  Ann Wu

发明人： Roger Spinti ,  Howard Tang ,  San-Ta Kow ,  Ann Wu

IPC分类号： G06F11/00

CPC分类号： G06F11/1417 ,  H03K19/17764 ,  H03K19/17772

摘要： In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preamble as the first bitstream is read from the non-volatile memory and before configuration data in the first bitstream is programmed into the volatile configuration memory. If a valid preamble is detected in the first bitstream, the controller programs the configuration memory with configuration data in the first bitstream. If a valid preamble is not detected in the first bitstream, the controller reads a second bitstream from a second memory block of the non-volatile memory.

摘要翻译： 在本发明的一个实施例中，可编程逻辑器件包括配置存储器和控制器。 控制器可以从非易失性存储器的第一存储器块读取第一比特流，并且检测第一比特流是否包含有效前同步码，因为第一比特流是从非易失性存储器读取的，并且在第一比特流中的配置数据被编程为 易失性配置存储器。 如果在第一比特流中检测到有效的前导码，则控制器使用第一比特流中的配置数据来对配置存储器进行编程。 如果在第一比特流中没有检测到有效的前导码，则控制器从非易失性存储器的第二存储器块读取第二比特流。

公开(公告)号：US07725803B1

公开(公告)日：2010-05-25

申请号：US11557808

申请日：2006-11-08

申请人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ann Wu

发明人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ann Wu

IPC分类号： H03M13/00 ,  G01R31/28

CPC分类号： H03K19/1776 ,  H03K19/17764 ,  H03M13/09

摘要： In accordance with an embodiment of the present invention, a programmable logic device includes configuration memory to store configuration data to configure the programmable logic device, and a non-volatile memory to store configuration data for transfer to the configuration memory to configure the programmable logic device. The non-volatile memory also stores a first code value based on the configuration data stored in the non-volatile memory. A code block calculates a second code value based on the configuration data transferred to the configuration memory. A comparator compares the first code value to the second code value to verify that the configuration data was not corrupted during the transfer from the non-volatile memory to the configuration memory.

摘要翻译： 根据本发明的实施例，可编程逻辑器件包括用于存储配置数据以配置可编程逻辑器件的配置存储器和用于存储用于传送到配置存储器的配置数据以配置可编程逻辑器件的非易失性存储器 。 非易失性存储器还存储基于存储在非易失性存储器中的配置数据的第一代码值。 代码块基于传送到配置存储器的配置数据来计算第二代码值。 比较器将第一代码值与第二代码值进行比较，以验证在从非易失性存储器传输到配置存储器期间配置数据未被破坏。

公开(公告)号：US07631223B1

公开(公告)日：2009-12-08

申请号：US11447591

申请日：2006-06-06

申请人： Roger Spinti ,  Howard Tang ,  San-Ta Kow ,  Ann Wu

发明人： Roger Spinti ,  Howard Tang ,  San-Ta Kow ,  Ann Wu

IPC分类号： G06F11/00

CPC分类号： G06F11/1417 ,  H03K19/17764 ,  H03K19/17772

摘要： Various techniques are disclosed herein to provide an improved approach to the loading of configuration data into configuration memory of programmable logic devices. For example, in accordance with one embodiment of the present invention a method of configuring a programmable logic device includes reading a first bitstream from a first memory block of an external memory device. The first bitstream is checked for errors and a second bitstream is read from a second memory block of the external memory device if an error is detected. Configuration memory of the programmable logic device is programmed with configuration data provided in one of the first bitstream and the second bitstream.

摘要翻译： 本文公开了各种技术以提供将配置数据加载到可编程逻辑器件的配置存储器中的改进方法。 例如，根据本发明的一个实施例，配置可编程逻辑器件的方法包括从外部存储器件的第一存储器块读取第一位流。 检查第一比特流的错误，并且如果检测到错误，则从外部存储器装置的第二存储器块读取第二比特流。 可编程逻辑器件的配置存储器被编程为在第一比特流和第二比特流之一中提供的配置数据。

公开(公告)号：US08108754B1

公开(公告)日：2012-01-31

申请号：US12786359

申请日：2010-05-24

申请人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ann Wu

发明人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ann Wu

IPC分类号： H03M13/00 ,  G01R31/28

CPC分类号： H03K19/1776 ,  H03K19/17764 ,  H03M13/09

摘要： In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes transferring the configuration data from non-volatile memory to configuration memory within the programmable logic device; calculating a code value based on the configuration data transferred from the non-volatile memory to the configuration memory; and comparing the calculated code value to the pre-calculated code value.

摘要翻译： 在一个实施例中，验证可编程逻辑器件的编程操作的方法包括在可编程逻辑器件配置数据内的非易失性存储器中存储和基于配置数据的预先计算的代码值。 该方法还包括将配置数据从非易失性存储器转移到可编程逻辑器件内的配置存储器; 基于从所述非易失性存储器传送到所述配置存储器的配置数据计算代码值; 以及将计算的代码值与预先计算的代码值进行比较。

公开(公告)号：US07876125B1

公开(公告)日：2011-01-25

申请号：US12464822

申请日：2009-05-12

申请人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ju Shen

发明人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ju Shen

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/17772 ,  H03K19/1776

摘要： Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.

摘要翻译： 根据本发明的一个或多个实施例，系统和方法为可编程逻辑器件提供寄存器数据保留技术。 例如，在一个实施例中，可编程逻辑器件包括适于在可编程逻辑器件的操作期间生成用户数据的多个逻辑块; 多个寄存器，适于在可编程逻辑器件的重新编程操作期间存储用户数据; 以及适于在逻辑块和寄存器之间提供编程数据路径的可配置路由资源。

公开(公告)号：US07535253B1

公开(公告)日：2009-05-19

申请号：US11941006

申请日：2007-11-15

申请人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ju Shen

发明人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ju Shen

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/17772 ,  H03K19/1776

摘要： Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment, a method includes programming routing resources between programmable logic and registers of a programmable logic device to provide a data path for data prior to a reprogramming; transferring data from the programmable logic, prior to the reprogramming, to the registers via the data path to store the data within the programmable logic device during the reprogramming; reprogramming the programmable logic device, wherein the reprogramming provides a reprogrammed data path between the programmable logic and the registers of the programmable logic device; and transferring the data within the programmable logic device from the registers via the reprogrammed data path for use by the programmable logic after the reprogramming of the programmable logic device has been completed.

摘要翻译： 根据本发明的一个或多个实施例，系统和方法为可编程逻辑器件提供寄存器数据保留技术。 例如，根据实施例，一种方法包括在可编程逻辑和可编程逻辑器件的寄存器之间编程路由资源，以在重新编程之前提供用于数据的数据路径; 在重新编程之前，通过数据路径将数据从可编程逻辑转移到寄存器，以便在重新编程期间将数据存储在可编程逻辑器件内; 重新编程可编程逻辑器件，其中重新编程在可编程逻辑器件和可编程逻辑器件的寄存器之间提供重新编程的数据通路; 并且在可编程逻辑器件的重新编程已经完成之后，通过可编程逻辑器件从寄存器传送数据以供可编程逻辑使用。

公开(公告)号：US07768300B1

公开(公告)日：2010-08-03

申请号：US12511388

申请日：2009-07-29

申请人： Howard Tang ,  Roger Spinti ,  San-Ta Kow

发明人： Howard Tang ,  Roger Spinti ,  San-Ta Kow

IPC分类号： H03K19/177 ,  G11C8/00

CPC分类号： H03K19/17776 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/17756

摘要： In one embodiment, a programmable logic device (PLD) includes a slave port and a master port. The slave port can receive a configuration data bitstream and a slave clock signal from a master port of a first external device. The master port can provide the configuration data bitstream and a master clock signal from the PLD to a slave port of a second external device. An interface block in the PLD can pass the configuration data bitstream from the slave port through the PLD to the master port. In another embodiment, a PLD includes a slave serial peripheral interface (SPI) port and configuration memory. The slave SPI port can receive a configuration data bitstream and a slave clock signal from a master SPI port of an external device. The configuration memory stores the received bitstream for configuring the PLD.

摘要翻译： 在一个实施例中，可编程逻辑器件（PLD）包括从端口和主端口。 从端口可以从第一外部设备的主端口接收配置数据比特流和从时钟信号。 主端口可以将配置数据比特流和来自PLD的主时钟信号提供给第二外部设备的从端口。 PLD中的接口块可以将配置数据比特流从从端口通过PLD传递到主端口。 在另一个实施例中，PLD包括从串行外设接口（SPI）端口和配置存储器。 从站SPI端口可以从外部设备的主SPI端口接收配置数据位流和从时钟信号。 配置存储器存储用于配置PLD的接收比特流。

公开(公告)号：US07570078B1

公开(公告)日：2009-08-04

申请号：US11761221

申请日：2007-06-11

申请人： Howard Tang ,  Roger Spinti ,  San-Ta Kow

发明人： Howard Tang ,  Roger Spinti ,  San-Ta Kow

IPC分类号： H03K19/177 ,  G11C8/00

CPC分类号： H03K19/17776 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/17756

摘要： Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). In one example, a method of operating a PLD includes receiving a configuration data bitstream at a slave serial peripheral interface (SPI) port of a PLD from a master SPI port of a first external device. The method also includes passing the configuration data bitstream through the PLD from the slave SPI port of the PLD to a master SPI port of the PLD. The method further includes providing the configuration data bitstream from the master SPI port of the PLD to a slave SPI port of a second external device.

摘要翻译： 本文公开了系统和方法，以提供诸如可编程逻辑器件（PLD）之类的集成电路的配置的改进方法。 在一个示例中，操作PLD的方法包括从第一外部设备的主SPI端口接收PLD的从串行外设接口（SPI）端口的配置数据比特流。 该方法还包括将配置数据比特流通过PLD从PLD的从SPI端口传递到PLD的主SPI端口。 该方法还包括将配置数据比特流从PLD的主SPI端口提供给第二外部设备的从SPI端口。

公开(公告)号：US07397274B1

公开(公告)日：2008-07-08

申请号：US11100718

申请日：2005-04-07

申请人： Howard Tang ,  Satwant Singh ,  San-Ta Kow

发明人： Howard Tang ,  Satwant Singh ,  San-Ta Kow

IPC分类号： H03K19/00 ,  G01R31/28

CPC分类号： H03K19/17744 ,  G01R31/318516 ,  G01R31/318544 ,  H03K19/17732

摘要： In one embodiment of the invention, a programmable logic device such as an FPGA includes a programmable fabric; a JTAG interface operable to receive configuration data for programming the fabric; a SPI interface operable to receive and transmit configuration data for programming the fabric; and circuitry coupled to the JTAG and SPI interfaces. The circuitry is operable, without being configured, to transfer configuration data received at the JTAG interface to the SPI interface for transmission to an external device having a SPI interface, such as a serial flash memory.

摘要翻译： 在本发明的一个实施例中，诸如FPGA的可编程逻辑器件包括可编程结构; JTAG接口，可操作用于接收用于编程织物的配置数据; SPI接口，可操作用于接收和发送用于编程织物的配置数据; 以及耦合到JTAG和SPI接口的电路。 电路可操作，而不被配置，将在JTAG接口处接收到的配置数据传送到SPI接口，以传输到具有诸如串行闪存等SPI接口的外部设备。

公开(公告)号：US07652500B1

公开(公告)日：2010-01-26

申请号：US12044842

申请日：2008-03-07

申请人： Howard Tang ,  Ju Shen ,  San-Ta Kow

发明人： Howard Tang ,  Ju Shen ,  San-Ta Kow

IPC分类号： H03K19/173

CPC分类号： H03K19/17772 ,  H03K19/17744 ,  H03K19/17764

摘要： Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks and corresponding input/output pins, and configuration memory. The PLD also includes registers adapted to capture output signal values of the input/output pins before a reconfiguration of the programmable logic device and to provide the captured values on the input/output pins during the reconfiguration of the PLD.

摘要翻译： 为可编程逻辑器件（PLD）提供了改进的重新配置技术。 例如，根据本发明的实施例，可编程逻辑器件包括逻辑块，输入/输出块和相应的输入/输出引脚和配置存储器。 PLD还包括适用于在可编程逻辑器件重新配置之前捕获输入/输出引脚的输出信号值并在PLD重新配置期间在输入/输出引脚上提供捕获值的寄存器。