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    Memory controller adaptable to multiple memory devices
    3.
    发明授权
    Memory controller adaptable to multiple memory devices 有权
    内存控制器适用于多个存储设备

    公开(公告)号：US09465728B2

    公开(公告)日：2016-10-11

    申请号：US12939135

    申请日：2010-11-03

    申请人： Howard Tsai ,  Dmitry Vyshetsky ,  Neal Meininger

    发明人： Howard Tsai ,  Dmitry Vyshetsky ,  Neal Meininger

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F13/16

    CPC分类号： G06F12/02 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1689 ,  G06F13/1694

    摘要： A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.

    摘要翻译： 在一个实施例中，存储器控制器包括命令转换数据结构，前端和后端。 命令翻译数据结构将命令操作映射到原语，其中原语从为一个或多个存储器件确定的命令操作中分解。 前端从处理单元接收命令操作，并且使用命令翻译数据结构将每个命令操作转换成一组一个或多个相应的原语。 后端将针对每个接收到的命令操作的一个或多个相应基元的集合输出到给定的存储器件。

    PROGRAMMABLE MEMORY CONTROLLER
    4.
    发明申请
    PROGRAMMABLE MEMORY CONTROLLER 有权
    可编程内存控制器

    公开(公告)号：US20120110242A1

    公开(公告)日：2012-05-03

    申请号：US12939135

    申请日：2010-11-03

    申请人： Howard Tsai ,  Dmitry Vyshetsky ,  Neal Meininger

    发明人： Howard Tsai ,  Dmitry Vyshetsky ,  Neal Meininger

    IPC分类号： G06F12/02

    CPC分类号： G06F12/02 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1689 ,  G06F13/1694

    摘要： A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.

    摘要翻译： 在一个实施例中，存储器控制器包括命令转换数据结构，前端和后端。 命令翻译数据结构将命令操作映射到原语，其中原语从为一个或多个存储器件确定的命令操作中分解。 前端从处理单元接收命令操作，并且使用命令翻译数据结构将每个命令操作转换成一组一个或多个相应的原语。 后端将针对每个接收到的命令操作的一个或多个相应基元的集合输出到给定的存储器件。

    METHOD AND SYSTEM FOR IMPROVED FLASH CONTROLLER COMMANDS SELECTION
    5.
    发明申请
    METHOD AND SYSTEM FOR IMPROVED FLASH CONTROLLER COMMANDS SELECTION 有权
    改进的闪存控制器命令选择的方法和系统

    公开(公告)号：US20100161941A1

    公开(公告)日：2010-06-24

    申请号：US12340380

    申请日：2008-12-19

    申请人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

    发明人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

    IPC分类号： G06F9/30 ,  G06F12/08

    CPC分类号： G06F13/1605 ,  G06F9/38

    摘要： A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.

    摘要翻译： 用于选择发出的闪速存储命令的子集以提高命令执行的处理时间的系统。 多个端口存储第一多个命令标识符并且与多个端口相关联。 第一多个仲裁器中的每一个在每个相应端口内的命令标识符之中选择最旧的命令标识符，导致第二多个命令标识符。 第二仲裁器基于命令标识符年龄和端口的优先级，从第二多个命令标识符中进行多个选择。 会话标识符队列存储与形成第三多个命令的其他命令中的与多个选择相关联的命令。 微控制器基于执行优化启发式方式从第三多个命令中选择可执行命令以执行。 执行该命令后，端口中的命令标识符被清除。

    MEMORY DEVICE WEAR-LEVELING TECHNIQUES
    6.
    发明申请
    MEMORY DEVICE WEAR-LEVELING TECHNIQUES 审中-公开
    内存设备磨损技术

    公开(公告)号：US20110161553A1

    公开(公告)日：2011-06-30

    申请号：US12649992

    申请日：2009-12-30

    申请人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Yen Lin

    发明人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Yen Lin

    IPC分类号： G06F12/06 ,  G06F12/00

    CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/7211

    摘要： The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access commands utilizing the cached persistent state parameters. When processing memory access commands, the logical block address and length parameter of a logical address of a command may be translated to a plurality of physical addresses for accessing one or more memory devices, each physical address includes a device address, a logical unit address, a block address, and a page address, wherein the block address includes one or more interleaved address bits.

    摘要翻译： 磨损均衡技术包括发现一个或多个存储器设备的持久状态，或者如果给定存储器设备未发现持久状态，则为给定存储器设备的每个逻辑单元构建和缓存持久状态参数。 这些技术还可以包括利用缓存的持久状态参数来处理存储器访问命令。 当处理存储器访问命令时，可以将命令的逻辑地址的逻辑块地址和长度参数转换为用于访问一个或多个存储器设备的多个物理地址，每个物理地址包括设备地址，逻辑单元地址， 块地址和页地址，其中块地址包括一个或多个交织地址位。

    Method and system for improved flash controller commands selection
    7.
    发明授权
    Method and system for improved flash controller commands selection 有权
    改进闪存控制器命令选择的方法和系统

    公开(公告)号：US09208108B2

    公开(公告)日：2015-12-08

    申请号：US12340380

    申请日：2008-12-19

    申请人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

    发明人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

    IPC分类号： G06F9/30 ,  G06F13/16 ,  G06F9/38

    CPC分类号： G06F13/1605 ,  G06F9/38

    摘要： A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.

    摘要翻译： 用于选择发出的闪速存储命令的子集以提高命令执行的处理时间的系统。 多个端口存储第一多个命令标识符并且与多个端口相关联。 第一多个仲裁器中的每一个在每个相应端口内的命令标识符之中选择最旧的命令标识符，导致第二多个命令标识符。 第二仲裁器基于命令标识符年龄和端口的优先级，从第二多个命令标识符中进行多个选择。 会话标识符队列存储与形成第三多个命令的其他命令中的与多个选择相关联的命令。 微控制器基于执行优化启发式方式从第三多个命令中选择可执行命令以执行。 执行该命令后，端口中的命令标识符被清除。

    Method and system for fast two bit error correction
    8.
    发明授权
    Method and system for fast two bit error correction 有权
    快速二位纠错的方法和系统

    公开(公告)号：US08683293B2

    公开(公告)日：2014-03-25

    申请号：US12639850

    申请日：2009-12-16

    申请人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Paul Gyugyi

    发明人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Paul Gyugyi

    IPC分类号： H03M13/00

    CPC分类号： H03M13/152 ,  H03M13/1575

    摘要： An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.

    摘要翻译： 用于纠正两位错误的错误定位器单元。 误差定位器单元包括多个操作单元，归一化基变换单元和转换单元。 多个操作单元基于伽罗瓦域的第一个基于所生成的校正子来计算多项式的系数。 对系数进行操作会在第一个基础上产生根定义值向量。 归一化基变换单元将根定义值向量变换为正常基，以产生多个根。 转换单元将多个根转换为第一基。 基于系数计算的缩放因子被应用于转换单元的输出，以在第一基础上产生用于所述多项式的多个缩放根。 添加多个缩放根以产生多项式的误差位置。

    METHOD AND SYSTEM FOR FAST TWO BIT ERROR CORRECTION
    9.
    发明申请
    METHOD AND SYSTEM FOR FAST TWO BIT ERROR CORRECTION 有权
    用于快速双位错误校正的方法和系统

    公开(公告)号：US20110145677A1

    公开(公告)日：2011-06-16

    申请号：US12639850

    申请日：2009-12-16

    申请人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Paul Gyugyi

    发明人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Paul Gyugyi

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/152 ,  H03M13/1575

    摘要： An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.

    摘要翻译： 用于纠正两位错误的错误定位器单元。 误差定位器单元包括多个操作单元，归一化基变换单元和转换单元。 多个操作单元基于伽罗瓦域的第一个基于所生成的校正子来计算多项式的系数。 对系数进行操作会在第一个基础上产生根定义值向量。 归一化基变换单元将根定义值向量变换为正常基，以产生多个根。 转换单元将多个根转换为第一基。 基于系数计算的缩放因子被应用于转换单元的输出，以在第一基础上产生用于所述多项式的多个缩放根。 添加多个缩放根以产生多项式的误差位置。

    Method and system for improving direct memory access offload
    10.
    发明授权
    Method and system for improving direct memory access offload 有权
    改进直接内存访问卸载的方法和系统

    公开(公告)号：US08732350B2

    公开(公告)日：2014-05-20

    申请号：US12340494

    申请日：2008-12-19

    申请人： Dmitry Vyshetski ,  Howard Tsai ,  Paul J. Gyugyi

    发明人： Dmitry Vyshetski ,  Howard Tsai ,  Paul J. Gyugyi

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： A system for improving direct memory access (DMA) offload. The system includes a processor, a data DMA engine and memory components. The processor selects an executable command comprising subcommands. The DDMA engine executes DMA operations related to a subcommand to perform memory transfer operations. The memory components store the plurality of subcommands and status data resulting from DMA operations. Each of the memory components has a corresponding token associated therewith. Possession of a token allocates its associated memory component to the processor or the DDMA engine possessing the token, making it inaccessible to the other. A first memory component and a second memory component of the plurality of memory components are used by the processor and the DDMA engine respectively and simultaneously. Tokens, e.g., the first and/or the second, are exchanged between the DDMA engine and the processor when the DDMA engine and/or the microcontroller complete accessing associated memory components.

    摘要翻译： 一种用于改善直接存储器访问（DMA）卸载的系统。 该系统包括处理器，数据DMA引擎和存储器组件。 处理器选择包含子命令的可执行命令。 DDMA引擎执行与子命令相关的DMA操作，以执行存储器传输操作。 存储器组件存储由DMA操作产生的多个子命令和状态数据。 每个存储器组件具有与其相关联的相应令牌。 拥有令牌将其相关的内存组件分配给处理器或拥有令牌的DDMA引擎，使其无法访问。 处理器和DDMA引擎分别和同时地使用多个存储器组件的第一存储器组件和第二存储器组件。 当DDMA引擎和/或微控制器完成访问相关的存储器组件时，例如第一和/或第二的令牌在DDMA引擎和处理器之间交换。