公开(公告)号：US09110714B2

公开(公告)日：2015-08-18

申请号：US12504313

申请日：2009-07-16

申请人： Alexander Joffe ,  Dmitry Vyshetsky

发明人： Alexander Joffe ,  Dmitry Vyshetsky

IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F9/48 ,  G06F9/38 ,  G06F9/52

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/52 ,  G06F2209/507

摘要： In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

公开(公告)号：US08694750B2

公开(公告)日：2014-04-08

申请号：US12339664

申请日：2008-12-19

申请人： Dmitry Vyshetsky ,  Paul Gyugyi

发明人： Dmitry Vyshetsky ,  Paul Gyugyi

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7211

摘要： Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.

摘要翻译： 本发明的实施例涉及一种用于允许在不改变应用固件的情况下在不同性能和成本的存储位置之间移动数据结构的方法和系统。 在一个实施例中，应用固件而不是应用固件直接访问存储器，应用程序固件通过参数来请求数据结构，实现返回指针。 参数可以是例如数据扇区的逻辑块地址，并且数据结构可以是该逻辑块地址（LBA）的映射和关联信息到闪存设备中的位置。

公开(公告)号：US20100161941A1

公开(公告)日：2010-06-24

申请号：US12340380

申请日：2008-12-19

申请人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

发明人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F13/1605 ,  G06F9/38

摘要： A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.

摘要翻译： 用于选择发出的闪速存储命令的子集以提高命令执行的处理时间的系统。 多个端口存储第一多个命令标识符并且与多个端口相关联。 第一多个仲裁器中的每一个在每个相应端口内的命令标识符之中选择最旧的命令标识符，导致第二多个命令标识符。 第二仲裁器基于命令标识符年龄和端口的优先级，从第二多个命令标识符中进行多个选择。 会话标识符队列存储与形成第三多个命令的其他命令中的与多个选择相关联的命令。 微控制器基于执行优化启发式方式从第三多个命令中选择可执行命令以执行。 执行该命令后，端口中的命令标识符被清除。

公开(公告)号：US20090150689A1

公开(公告)日：2009-06-11

申请号：US12342865

申请日：2008-12-23

申请人： Brad W. Simeral ,  David C. Reed ,  Dmitry Vyshetsky ,  Roman Surgutchick ,  Robert William Chapman ,  Joshua Titus ,  Anand Srinivasan ,  Hari U. Krishnan

发明人： Brad W. Simeral ,  David C. Reed ,  Dmitry Vyshetsky ,  Roman Surgutchick ,  Robert William Chapman ,  Joshua Titus ,  Anand Srinivasan ,  Hari U. Krishnan

IPC分类号： G06F1/32

CPC分类号： G06F1/28 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component. It also includes a controller for adjusting operational characteristics of the component for modifying the power consumed by the component to comply with a performance profile, which generally specifies permissible power consumption levels for the component.

摘要翻译： 公开了一种数据路径控制器，计算机设备，装置和方法，用于将电源管理功能集成到数据路径控制器中，以管理由处理器和外围设备消耗的功率。 通过在数据路径控制器内部嵌入电源管理，数据路径控制器可以有利地在现场修改其标准，使得其能够根据处理器和外围设备的变化来适应其功率管理动作。 此外，数据路径控制器包括功率管理接口，其提供用于监视和/或量化各种组件的功耗的功率监控端口。 在一个实施例中，数据路径控制器包括用于可选地监视组件的功率的功率监视接口。 它还包括用于调整部件的操作特性的控制器，用于修改部件消耗的功率以符合性能曲线，其通常指定部件的允许功率消耗水平。

公开(公告)号：US06330584B1

公开(公告)日：2001-12-11

申请号：US09055033

申请日：1998-04-03

申请人： Alexander Joffe ,  Dmitry Vyshetsky

发明人： Alexander Joffe ,  Dmitry Vyshetsky

IPC分类号： G06F900

CPC分类号： G06F9/5011 ,  G06F9/3851 ,  G06F9/462 ,  G06F9/4881 ,  G06F2209/507

摘要： In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

摘要翻译： 在多任务流水线处理器中，连续的指令由不同的任务执行，消除了当前一条指令无法完成时清除随后指令的指令执行流水线的需要。 任务不共享存储任务特定值的寄存器，因此在新任务计划执行时不需要保存或加载寄存器。 如果指令访问不可用资源，则指令将被暂停，从而允许执行其他任务的指令，直到资源变为可用。 任务调度由硬件执行; 不需要操作系统。 提供简单的技术来同步不同任务之间的共享资源访问。

公开(公告)号：US09465728B2

公开(公告)日：2016-10-11

申请号：US12939135

申请日：2010-11-03

申请人： Howard Tsai ,  Dmitry Vyshetsky ,  Neal Meininger

发明人： Howard Tsai ,  Dmitry Vyshetsky ,  Neal Meininger

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F13/16

CPC分类号： G06F12/02 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1689 ,  G06F13/1694

摘要： A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.

摘要翻译： 在一个实施例中，存储器控制器包括命令转换数据结构，前端和后端。 命令翻译数据结构将命令操作映射到原语，其中原语从为一个或多个存储器件确定的命令操作中分解。 前端从处理单元接收命令操作，并且使用命令翻译数据结构将每个命令操作转换成一组一个或多个相应的原语。 后端将针对每个接收到的命令操作的一个或多个相应基元的集合输出到给定的存储器件。

公开(公告)号：US20110161553A1

公开(公告)日：2011-06-30

申请号：US12649992

申请日：2009-12-30

申请人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Yen Lin

发明人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Yen Lin

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/7211

摘要： The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access commands utilizing the cached persistent state parameters. When processing memory access commands, the logical block address and length parameter of a logical address of a command may be translated to a plurality of physical addresses for accessing one or more memory devices, each physical address includes a device address, a logical unit address, a block address, and a page address, wherein the block address includes one or more interleaved address bits.

摘要翻译： 磨损均衡技术包括发现一个或多个存储器设备的持久状态，或者如果给定存储器设备未发现持久状态，则为给定存储器设备的每个逻辑单元构建和缓存持久状态参数。 这些技术还可以包括利用缓存的持久状态参数来处理存储器访问命令。 当处理存储器访问命令时，可以将命令的逻辑地址的逻辑块地址和长度参数转换为用于访问一个或多个存储器设备的多个物理地址，每个物理地址包括设备地址，逻辑单元地址， 块地址和页地址，其中块地址包括一个或多个交织地址位。

公开(公告)号：US07562205B1

公开(公告)日：2009-07-14

申请号：US11844248

申请日：2007-08-23

申请人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

发明人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

IPC分类号： G06F12/00

CPC分类号： G06F12/1036

摘要： A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

摘要翻译： 虚拟地址转换表和片上地址缓存可用于将虚拟地址转换为物理地址。 使用与一些范围的虚拟地址相关联的集群提供地址转换信息，该集群可用于将其范围中的任何虚拟地址转换为物理地址，其中由不同集群映射的范围的大小可能不同。 集群存储在由虚拟地址索引的地址转换表中，以便从任何有效的虚拟地址开始，可以从转换表中检索用于转换该地址的适当集群。 最近检索的群集存储在片上缓存中，并且可以使用高速缓存的群集来翻译其范围内的任何虚拟地址，而不再重新访问地址转换表。

公开(公告)号：US07278008B1

公开(公告)日：2007-10-02

申请号：US10769357

申请日：2004-01-30

申请人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

发明人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

IPC分类号： G06F12/00

CPC分类号： G06F12/1036

摘要： A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

摘要翻译： 虚拟地址转换表和片上地址缓存可用于将虚拟地址转换为物理地址。 使用与一些范围的虚拟地址相关联的集群提供地址转换信息，该集群可用于将其范围中的任何虚拟地址转换为物理地址，其中由不同集群映射的范围的大小可能不同。 集群存储在由虚拟地址索引的地址转换表中，以便从任何有效的虚拟地址开始，可以从转换表中检索用于转换该地址的适当集群。 最近检索的群集存储在片上缓存中，并且可以使用高速缓存的群集来翻译其范围内的任何虚拟地址，而不再重新访问地址转换表。

公开(公告)号：US06307860B1

公开(公告)日：2001-10-23

申请号：US09055044

申请日：1998-04-03

申请人： Alexander Joffe ,  Dmitry Vyshetsky

发明人： Alexander Joffe ,  Dmitry Vyshetsky

IPC分类号： H04L1228

CPC分类号： H04L49/3081 ,  H04L12/5601 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/351 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5665 ,  H04Q11/0478

摘要： A processor system suitable to provide an interface between networks includes a software programmable processor and a channel processor that receives data from a network and transforms data at commands from the software programmable processor. The channel can execute only a few simple commands, but these commands are sufficient for a wide range of systems. The commands include (1) a command to transmit received data, perhaps skipping some data; and (2) a command to transmit data specified by the command itself rather than the received data. The channel is fast, simple and inexpensive.

摘要翻译： 适于提供网络之间的接口的处理器系统包括软件可编程处理器和从网络接收数据并以来自软件可编程处理器的命令转换数据的通道处理器。 该通道只能执行几个简单的命令，但这些命令对于广泛的系统是足够的。 命令包括（1）发送接收数据的命令，可能跳过一些数据; 和（2）用于发送由命令本身指定的数据而不是接收到的数据的命令。 频道快速，简单，便宜。