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69 条记录 (耗时 0.042 秒)

    Method and System For Making Photo-Resist Patterns
    7.
    发明申请
    Method and System For Making Photo-Resist Patterns 审中-公开
    制作防光图案的方法和系统

    公开(公告)号：US20080102648A1

    公开(公告)日：2008-05-01

    申请号：US11555558

    申请日：2006-11-01

    申请人： Chin-Hsiang Lin ,  Hsiao-Tzu Lu ,  Kuei Shun Chen ,  Ching-Yu Chang ,  Vencent Chang

    发明人： Chin-Hsiang Lin ,  Hsiao-Tzu Lu ,  Kuei Shun Chen ,  Ching-Yu Chang ,  Vencent Chang

    IPC分类号： H01L21/302 ,  G03G13/10

    CPC分类号： H01L21/0271 ,  G03F7/095

    摘要： A method of forming a resist pattern in a semiconductor device layer includes forming a buffer layer on a semiconductor device layer and forming a resist layer on the buffer layer. A decomposing agent is released into a portion of the buffer layer by a portion of the resist layer whereupon the portion of the buffer layer and the portion of the resist layer are removed to form a process window substantially free of resist residue that can be subsequently exploited for etching of the semiconductor device layer.

    摘要翻译： 在半导体器件层中形成抗蚀剂图案的方法包括在半导体器件层上形成缓冲层，并在缓冲层上形成抗蚀剂层。 分解剂通过抗蚀剂层的一部分释放到缓冲层的一部分中，随后缓冲层的部分和抗蚀剂层的一部分被去除以形成基本上不含抗蚀剂残留物的工艺窗口，其可以被随后利用 用于蚀刻半导体器件层。

    Field effect transistors and method of forming the same
    9.
    发明授权
    Field effect transistors and method of forming the same 有权
    场效应晶体管及其形成方法

    公开(公告)号：US08969922B2

    公开(公告)日：2015-03-03

    申请号：US13368960

    申请日：2012-02-08

    申请人： Chia-Chu Liu ,  Kuei Shun Chen ,  Mu-Chi Chiang ,  Yao-Kwang Wu ,  Bi-Fen Wu ,  Huan-Just Lin ,  Hsiao-Tzu Lu ,  Hui-Chi Huang

    发明人： Chia-Chu Liu ,  Kuei Shun Chen ,  Mu-Chi Chiang ,  Yao-Kwang Wu ,  Bi-Fen Wu ,  Huan-Just Lin ,  Hsiao-Tzu Lu ,  Hui-Chi Huang

    IPC分类号： H01L27/118 ,  H01L29/66

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871

    摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

    摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括半导体衬底，其包括设置在第一器件区域中的第一器件，所述第一器件包括第一栅极结构，形成在第一栅极结构的侧壁上的第一栅极间隔物，以及第一源极和漏极特征， 设置在第二器件区域中，第二器件包括第二栅极结构，形成在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 半导体器件还包括设置在第一和第二栅极间隔物上的接触蚀刻停止层（CESL）和布置在第一和第二源极和漏极特征上的互连结构。 互连结构与第一和第二源极和漏极特征电接触并与CESL接触。

    Semiconductor Device and Method of Forming the Same
    10.
    发明申请
    Semiconductor Device and Method of Forming the Same 有权
    半导体器件及其形成方法

    公开(公告)号：US20130200461A1

    公开(公告)日：2013-08-08

    申请号：US13368960

    申请日：2012-02-08

    申请人： Chia-Chu Liu ,  Kuei Shun Chen ,  Mu-Chi Chiang ,  Yao-Kwang Wu ,  Bi-Fen Wu ,  Huan-Just Lin ,  Hsiao-Tzu Lu ,  Hui-Chi Huang

    发明人： Chia-Chu Liu ,  Kuei Shun Chen ,  Mu-Chi Chiang ,  Yao-Kwang Wu ,  Bi-Fen Wu ,  Huan-Just Lin ,  Hsiao-Tzu Lu ,  Hui-Chi Huang

    IPC分类号： H01L27/092 ,  H01L21/768

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871

    摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

    摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括半导体衬底，其包括设置在第一器件区域中的第一器件，所述第一器件包括第一栅极结构，形成在第一栅极结构的侧壁上的第一栅极间隔物，以及第一源极和漏极特征， 设置在第二器件区域中，第二器件包括第二栅极结构，形成在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 半导体器件还包括设置在第一和第二栅极间隔物上的接触蚀刻停止层（CESL）和布置在第一和第二源极和漏极特征上的互连结构。 互连结构与第一和第二源极和漏极特征电接触并与CESL接触。