摘要:
A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.
摘要:
A graphics processing unit (“GPU”) is configured to receive an interrupt command from a CPU or internal interrupt event while the GPU is processing a first context. The GPU saves the first context to memory and records a precise processing position for the first context corresponding to the point interrupted. Thereafter, the GPU loads a second context to the processing portion of the GPU from memory and begins executing instructions associated with the second context. After the second context is complete of if an interrupt command directs restoration of the first context, the GPU's processor switches to the first context for continued processing. The first context is retrieved from memory and restored to the precise processing position where previously interrupted. The GPU then processes a remainder portion of the first context from the precise processing point to an end of the first context.
摘要:
A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.
摘要:
A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.
摘要:
A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an interrupt signal on a communication path from to a plurality of pipeline processing blocks in a graphics pipeline. A token, which corresponds to an end of an interrupted context, is forwarded from the command processor to a first pipeline processing block and subsequently to other pipeline blocks in the graphics pipeline. Each pipeline processing block discards contents of associated memory units upon receipt of the interrupt signal until the token is reached. The token may be forwarded to one or more additional pipeline processing blocks and memory units so that the token is communicated throughout the graphics pipeline to flush data associated with the first context. Data associated with the second context may follow behind the token through graphics pipeline.
摘要:
A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an interrupt signal on a communication path from to a plurality of pipeline processing blocks in a graphics pipeline. A token, which corresponds to an end of an interrupted context, is forwarded from the command processor to a first pipeline processing block and subsequently to other pipeline blocks in the graphics pipeline. Each pipeline processing block discards contents of associated memory units upon receipt of the interrupt signal until the token is reached. The token may be forwarded to one or more additional pipeline processing blocks and memory units so that the token is communicated throughout the graphics pipeline to flush data associated with the first context. Data associated with the second context may follow behind the token through graphics pipeline.
摘要:
A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.
摘要:
A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command so that multiple programs can be executed by the GPU. The CPU creates and the GPU stores a run list containing a plurality of contexts for execution, where each context has a ring buffer of commands and pointers for processing. The GPU initiates processing of a first context in the run list and retrieves memory access commands and pointers referencing data associated with the first context. The GPU's pipeline processes data associated with first context until empty or interrupted. If emptied, the GPU switches to a next context in the run list for processing data associated with that next context. When the last context in the run list is completed, the GPU may switch to another run list containing a new list of contexts for processing.
摘要:
A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command so that multiple programs can be executed by the GPU. The CPU creates and the GPU stores a run list containing a plurality of contexts for execution, where each context has a ring buffer of commands and pointers for processing. The GPU initiates processing of a first context in the run list and retrieves memory access commands and pointers referencing data associated with the first context. The GPU's pipeline processes data associated with first context until empty or interrupted. If emptied, the GPU switches to a next context in the run list for processing data associated with that next context. When the last context in the run list is completed, the GPU may switch to another run list containing a new list of contexts for processing.
摘要:
A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that arc also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.