GPU pipeline multiple level synchronization controller processor and method
    1.
    发明授权
    GPU pipeline multiple level synchronization controller processor and method 有权
    GPU管道多级同步控制器处理器和方法

    公开(公告)号:US07737983B2

    公开(公告)日:2010-06-15

    申请号:US11552693

    申请日:2006-10-25

    IPC分类号: G06F1/20 G06T1/00

    摘要: A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.

    摘要翻译: 一种用于应用程序和图形流水线之间的高级别同步的方法包括:在由中央处理单元发送的诸如命令流处理器(CSP)的预定组件的输入流中接收应用程序指令。 CSP可以具有耦合到图形流水线中的下一个组件的第一部分和耦合到图形流水线的多个组件的第二部分。 与应用指令相关联的命令可以从第一部分转发到图形流水线中的下一个组件或与其耦合的一些其它组件。 该命令可以被接收并且此后被执行。 响应可以在反馈路径上传送到CSP的第二部分。 可以由CSP接收和执行的非限制性示例性应用指令包括检查表面故障,陷阱,等待,信号,失速,翻转和触发。

    Interruptible GPU and method for context saving and restoring
    2.
    发明授权
    Interruptible GPU and method for context saving and restoring 有权
    中断GPU和上下文保存和恢复方法

    公开(公告)号:US07545381B2

    公开(公告)日:2009-06-09

    申请号:US11272356

    申请日:2005-11-10

    IPC分类号: G06T1/00 G06F9/46 G06T1/20

    CPC分类号: G06T15/005 G06F9/461 G06T1/20

    摘要: A graphics processing unit (“GPU”) is configured to receive an interrupt command from a CPU or internal interrupt event while the GPU is processing a first context. The GPU saves the first context to memory and records a precise processing position for the first context corresponding to the point interrupted. Thereafter, the GPU loads a second context to the processing portion of the GPU from memory and begins executing instructions associated with the second context. After the second context is complete of if an interrupt command directs restoration of the first context, the GPU's processor switches to the first context for continued processing. The first context is retrieved from memory and restored to the precise processing position where previously interrupted. The GPU then processes a remainder portion of the first context from the precise processing point to an end of the first context.

    摘要翻译: 图形处理单元(“GPU”)被配置为在GPU处理第一上下文时从CPU或内部中断事件接收中断命令。 GPU将第一上下文保存到存储器,并记录与中断点相对应的第一上下文的精确处理位置。 此后,GPU从存储器将第二上下文加载到GPU的处理部分,并开始执行与第二上下文相关联的指令。 在第二个上下文完成之后,如果中断命令指示第一个上下文的恢复,则GPU的处理器切换到第一上下文以继续处理。 第一个上下文从存储器中检索并恢复到之前中断的精确处理位置。 然后,GPU处理从精确处理点到第一上下文结束的第一上下文的余数部分。

    GPU Pipeline Multiple Level Synchronization Controller Processor and Method
    3.
    发明申请
    GPU Pipeline Multiple Level Synchronization Controller Processor and Method 有权
    GPU管道多级同步控制器处理器和方法

    公开(公告)号:US20070091102A1

    公开(公告)日:2007-04-26

    申请号:US11552693

    申请日:2006-10-25

    IPC分类号: G06T1/20

    摘要: A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.

    摘要翻译: 一种用于应用程序和图形流水线之间的高级别同步的方法包括:在由中央处理单元发送的诸如命令流处理器(CSP)的预定组件的输入流中接收应用程序指令。 CSP可以具有耦合到图形流水线中的下一个组件的第一部分和耦合到图形流水线的多个组件的第二部分。 与应用指令相关联的命令可以从第一部分转发到图形流水线中的下一个组件或与其耦合的一些其它组件。 该命令可以被接收并且此后被执行。 响应可以在反馈路径上传送到CSP的第二部分。 可以由CSP接收和执行的非限制性示例性应用指令包括检查表面故障,陷阱,等待,信号,失速,翻转和触发。

    GPU pipeline synchronization and control system and method
    4.
    发明授权
    GPU pipeline synchronization and control system and method 有权
    GPU流水线同步控制系统及方法

    公开(公告)号:US08817029B2

    公开(公告)日:2014-08-26

    申请号:US11468435

    申请日:2006-08-30

    摘要: A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.

    摘要翻译: 配置为根据信号和令牌同步数据处理的图形管线具有至少四个组件。 第一个组件具有一个输入和一个输出,并且在接收输入上的令牌,内部事件发生或输入路径上的信号接收之后传送输出令牌或有线信号。 第二分量具有一个输入和多个输出,并且在输入上接收令牌,内部事件发生或输入路径上的信号接收之后,在输出之一上传送令牌或有线信号。 第三组件具有多个输入和一个输出,并且在输入之一上接收令牌,内部事件发生或输入路径上的信号接收之后,在输出端上传送令牌或有线信号。 第四组件具有多个输入和多个输出,并且具有第三和第四组件的能力。

    Graphics pipeline precise interrupt method and apparatus
    5.
    发明授权
    Graphics pipeline precise interrupt method and apparatus 有权
    图形管道精确中断方法和装置

    公开(公告)号:US07583268B2

    公开(公告)日:2009-09-01

    申请号:US11272220

    申请日:2005-11-10

    CPC分类号: G06T1/20

    摘要: A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an interrupt signal on a communication path from to a plurality of pipeline processing blocks in a graphics pipeline. A token, which corresponds to an end of an interrupted context, is forwarded from the command processor to a first pipeline processing block and subsequently to other pipeline blocks in the graphics pipeline. Each pipeline processing block discards contents of associated memory units upon receipt of the interrupt signal until the token is reached. The token may be forwarded to one or more additional pipeline processing blocks and memory units so that the token is communicated throughout the graphics pipeline to flush data associated with the first context. Data associated with the second context may follow behind the token through graphics pipeline.

    摘要翻译: 图形处理单元(“GPU”)被配置为中断第一上下文的处理并根据命令启动对第二上下文的处理。 命令处理器在图形管线中的多个流水线处理块的通信路径上传送中断信号。 对应于中断上下文的结束的令牌从命令处理器转发到第一流水线处理块,并且随后传送到图形管线中的其他流水线块。 每个流水线处理块在接收到中断信号后丢弃相关存​​储器单元的内容,直到达到令牌。 令牌可以被转发到一个或多个附加流水线处理块和存储器单元,使得令牌在整个图形流水线中被通信以刷新与第一上下文相关联的数据。 与第二个上下文关联的数据可能通过图形流水线跟随令牌。

    Graphics pipeline precise interrupt method and apparatus
    6.
    发明申请
    Graphics pipeline precise interrupt method and apparatus 有权
    图形管道精确中断方法和装置

    公开(公告)号:US20070103474A1

    公开(公告)日:2007-05-10

    申请号:US11272220

    申请日:2005-11-10

    IPC分类号: G06T1/20

    CPC分类号: G06T1/20

    摘要: A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an interrupt signal on a communication path from to a plurality of pipeline processing blocks in a graphics pipeline. A token, which corresponds to an end of an interrupted context, is forwarded from the command processor to a first pipeline processing block and subsequently to other pipeline blocks in the graphics pipeline. Each pipeline processing block discards contents of associated memory units upon receipt of the interrupt signal until the token is reached. The token may be forwarded to one or more additional pipeline processing blocks and memory units so that the token is communicated throughout the graphics pipeline to flush data associated with the first context. Data associated with the second context may follow behind the token through graphics pipeline.

    摘要翻译: 图形处理单元(“GPU”)被配置为中断第一上下文的处理并根据命令启动对第二上下文的处理。 命令处理器在图形管线中的多个流水线处理块的通信路径上传送中断信号。 对应于中断上下文的结束的令牌从命令处理器转发到第一流水线处理块,随后转发到图形流水线中的其他流水线块。 每个流水线处理块在接收到中断信号后丢弃相关存​​储器单元的内容,直到达到令牌。 令牌可以被转发到一个或多个附加流水线处理块和存储器单元,使得令牌在整个图形流水线中被通信以刷新与第一上下文相关联的数据。 与第二个上下文关联的数据可能通过图形流水线跟随令牌。

    GPU Pipeline Synchronization and Control System and Method
    7.
    发明申请
    GPU Pipeline Synchronization and Control System and Method 有权
    GPU管线同步与控制系统与方法

    公开(公告)号:US20070091100A1

    公开(公告)日:2007-04-26

    申请号:US11468435

    申请日:2006-08-30

    IPC分类号: G06T1/20

    摘要: A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.

    摘要翻译: 配置为根据信号和令牌同步数据处理的图形管线具有至少四个组件。 第一个组件具有一个输入和一个输出,并且在接收输入上的令牌,内部事件发生或输入路径上的信号接收之后传送输出令牌或有线信号。 第二分量具有一个输入和多个输出,并且在输入上接收令牌,内部事件发生或输入路径上的信号接收之后,在输出之一上传送令牌或有线信号。 第三组件具有多个输入和一个输出,并且在输入之一上接收令牌,内部事件发生或输入路径上的信号接收之后,在输出端上传送令牌或有线信号。 第四组件具有多个输入和多个输出,并且具有第三和第四组件的能力。

    Interruptible GPU and method for processing multiple contexts and runlists
    8.
    发明授权
    Interruptible GPU and method for processing multiple contexts and runlists 有权
    可中断GPU和处理多个上下文和运行列表的方法

    公开(公告)号:US07580040B2

    公开(公告)日:2009-08-25

    申请号:US11271169

    申请日:2005-11-10

    IPC分类号: G06T1/00 G06T1/20 G06F9/46

    CPC分类号: G06T15/005

    摘要: A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command so that multiple programs can be executed by the GPU. The CPU creates and the GPU stores a run list containing a plurality of contexts for execution, where each context has a ring buffer of commands and pointers for processing. The GPU initiates processing of a first context in the run list and retrieves memory access commands and pointers referencing data associated with the first context. The GPU's pipeline processes data associated with first context until empty or interrupted. If emptied, the GPU switches to a next context in the run list for processing data associated with that next context. When the last context in the run list is completed, the GPU may switch to another run list containing a new list of contexts for processing.

    摘要翻译: 图形处理单元(“GPU”)被配置为中断第一上下文的处理并且在命令时启动对第二上下文的处理,使得可以由GPU执行多个程序。 CPU创建并且GPU存储包含用于执行的多个上下文的运行列表,其中每个上下文具有用于处理的命令的环形缓冲区和指针。 GPU启动处理运行列表中的第一上下文,并且检索引用与第一上下文相关联的数据的存储器访问命令和指针。 GPU的流水线处理与第一个上下文关联的数据,直到空或中断。 如果清空,则GPU切换到运行列表中的下一个上下文,以处理与该下一个上下文相关联的数据。 当运行列表中的最后一个上下文完成时,GPU可能切换到另一个运行列表,其中包含新的上下文列表以供处理。

    Interruptible GPU and method for processing multiple contexts and runlists
    9.
    发明申请
    Interruptible GPU and method for processing multiple contexts and runlists 有权
    可中断GPU和处理多个上下文和运行列表的方法

    公开(公告)号:US20070103475A1

    公开(公告)日:2007-05-10

    申请号:US11271169

    申请日:2005-11-10

    IPC分类号: G06T15/00

    CPC分类号: G06T15/005

    摘要: A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command so that multiple programs can be executed by the GPU. The CPU creates and the GPU stores a run list containing a plurality of contexts for execution, where each context has a ring buffer of commands and pointers for processing. The GPU initiates processing of a first context in the run list and retrieves memory access commands and pointers referencing data associated with the first context. The GPU's pipeline processes data associated with first context until empty or interrupted. If emptied, the GPU switches to a next context in the run list for processing data associated with that next context. When the last context in the run list is completed, the GPU may switch to another run list containing a new list of contexts for processing.

    摘要翻译: 图形处理单元(“GPU”)被配置为中断第一上下文的处理并且在命令时启动对第二上下文的处理,使得可以由GPU执行多个程序。 CPU创建并且GPU存储包含用于执行的多个上下文的运行列表,其中每个上下文具有用于处理的命令的环形缓冲区和指针。 GPU启动处理运行列表中的第一上下文,并且检索引用与第一上下文相关联的数据的存储器访问命令和指针。 GPU的流水线处理与第一个上下文关联的数据,直到空或中断。 如果清空,则GPU切换到运行列表中的下一个上下文,以处理与该下一个上下文相关联的数据。 当运行列表中的最后一个上下文完成时,GPU可能切换到另一个运行列表,其中包含新的上下文列表以供处理。

    Graphics Input Command Stream Scheduling Method and Apparatus
    10.
    发明申请
    Graphics Input Command Stream Scheduling Method and Apparatus 有权
    图形输入命令流调度方法和装置

    公开(公告)号:US20070091101A1

    公开(公告)日:2007-04-26

    申请号:US11530052

    申请日:2006-09-08

    IPC分类号: G06T1/20

    摘要: A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that arc also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.

    摘要翻译: GPU中的命令解析器被配置为调度所接收命令的执行,并且包括耦合到调度器的第一输入。 第一个命令解析器输入被配置为将总线接口命令传递给命令解析器以供执行。 第二命令解析器输入耦合到控制器,该控制器从由调度器接收环形缓冲器命令,与由命令解析器执行的新的或先前部分执行的环形缓冲器或上下文相关联。 第三个命令解析器输入耦合到命令DMA组件,该组件接收来自控制器的DMA命令,该命令也包含在新的或先前部分执行的环形缓冲器中,这些命令被转发到命令解析器以供执行。 命令解析器经由一个或多个输出转发对应于在一个或多个第一,第二和第三输入上接收的命令的数据。