公开(公告)号：US20120248574A1

公开(公告)日：2012-10-04

申请号：US13073848

申请日：2011-03-28

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L29/70 ,  H01L21/328

CPC分类号： H01L27/0259

摘要： A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.

摘要翻译： 提供了一种半导体结构及其制造方法及其操作方法。 半导体结构包括第一阱区，第二阱区，第一掺杂区，第二掺杂区，阳极和阴极。 第二阱区域与第一阱区域相邻。 第一掺杂区位于第二阱区上。 第二掺杂区域在第一阱区域上。 阳极耦合到第一掺杂区域和第二阱区域。 阴极耦合到第一阱区和第二掺杂区。 第一阱区和第一掺杂区具有第一导电类型。 第二阱区和第二掺杂区具有与第一导电类型相反的第二导电类型。

公开(公告)号：US08648386B2

公开(公告)日：2014-02-11

申请号：US13222187

申请日：2011-08-31

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/07

CPC分类号： H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

摘要： A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

摘要翻译： 提供其半导体结构及其制造方法以及ESD电路。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区和电阻。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第三掺杂区域具有第一类型的导电性。 第一掺杂区域和第三掺杂区域被第二掺杂区域分开。 电阻器耦合在第二掺杂区域和第三掺杂区域之间。 阳极耦合到第一掺杂区域。 阴极耦合到第三掺杂区域。

公开(公告)号：US20130049067A1

公开(公告)日：2013-02-28

申请号：US13222187

申请日：2011-08-31

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/07 ,  H01L21/331

CPC分类号： H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

摘要： A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

摘要翻译： 提供其半导体结构及其制造方法以及ESD电路。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区和电阻。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第三掺杂区域具有第一类型的导电性。 第一掺杂区域和第三掺杂区域被第二掺杂区域分开。 电阻器耦合在第二掺杂区域和第三掺杂区域之间。 阳极耦合到第一掺杂区域。 阴极耦合到第三掺杂区域。

公开(公告)号：US08519434B2

公开(公告)日：2013-08-27

申请号：US13053920

申请日：2011-03-22

申请人： Hsin-Liang Chen ,  Shou-Lun Tu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Shou-Lun Tu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L23/60

CPC分类号： H01L27/0259 ,  H01L29/1087

摘要： An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection.

摘要翻译： 静电放电（ESD）保护器件可以包括衬底，对应于衬底的第一部分设置并且具有设置在其表面上的两个N +段的N型阱区，邻近于衬底的P型阱区域 具有P +段和N +段的第二部分。 两个N +段可以彼此间隔开，并且每个可以各自与装置的阳极相关联。 N +段可以与器件的阴极相关联。 触点可以位于两个N +段之间的空间中并且连接到P +段。 接触可能形成寄生电容，结合与N +段相关联的寄生电阻，提供高电压ESD保护的自检。

公开(公告)号：US20120241900A1

公开(公告)日：2012-09-27

申请号：US13053920

申请日：2011-03-22

申请人： Hsin-Liang Chen ,  Shou-Lun Tu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Shou-Lun Tu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L27/0259 ,  H01L29/1087

摘要： An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection.

摘要翻译： 静电放电（ESD）保护器件可以包括衬底，对应于衬底的第一部分设置并且具有设置在其表面上的两个N +段的N型阱区，邻近于 具有P +段和N +段的第二部分。 两个N +段可以彼此间隔开，并且每个可以各自与装置的阳极相关联。 N +段可以与器件的阴极相关联。 触点可以位于两个N +段之间的空间中并且连接到P +段。 接触可能形成寄生电容，结合与N +段相关联的寄生电阻，提供高电压ESD保护的自检。

公开(公告)号：US08546917B2

公开(公告)日：2013-10-01

申请号：US13073848

申请日：2011-03-28

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/082 ,  H01L21/8249 ,  H01L21/8224 ,  H01L21/331

CPC分类号： H01L27/0259

摘要： A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.

摘要翻译： 提供了一种半导体结构及其制造方法及其操作方法。 半导体结构包括第一阱区，第二阱区，第一掺杂区，第二掺杂区，阳极和阴极。 第二阱区域与第一阱区域相邻。 第一掺杂区位于第二阱区上。 第二掺杂区域在第一阱区域上。 阳极耦合到第一掺杂区域和第二阱区域。 阴极耦合到第一阱区和第二掺杂区。 第一阱区和第一掺杂区具有第一导电类型。 第二阱区和第二掺杂区具有与第一导电类型相反的第二导电类型。

公开(公告)号：US08669639B2

公开(公告)日：2014-03-11

申请号：US13493311

申请日：2012-06-11

申请人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

发明人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

IPC分类号： H01L29/735

CPC分类号： H01L21/8224 ,  H01L27/0259 ,  H01L27/082 ,  H01L29/402 ,  H01L29/735 ,  H01L29/861

摘要： A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

摘要翻译： 提供半导体元件及其制造方法及其操作方法。 半导体元件包括衬底，第一阱，第二阱，第三阱，第四阱，底层，第一重掺杂区，第二重掺杂区，第三重掺杂区和场平面。 第一井，底层和第二井围绕第三井，用于浮置第三井和衬底。 第一，第二和第三重掺杂区域分别设置在第一，第二和第三阱中。 场板设置在第一井和第四井之间的连接点的上方。

公开(公告)号：US09029952B2

公开(公告)日：2015-05-12

申请号：US13450888

申请日：2012-04-19

申请人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

发明人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

IPC分类号： H01L27/14 ,  H01L29/66 ,  H01L29/735 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/6625 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/404 ,  H01L29/735

摘要： A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

摘要翻译： 半导体结构包括衬底，具有第一导电类型的第一阱，具有第二导电类型的第二阱，体区，第一掺杂区，第二掺杂区，第三掺杂区和场板。 在衬底中形成第一和第二阱。 身体区域形成在第二孔中。 第一和第二掺杂区分别形成在第一阱和体区中。 第二掺杂区域和第一掺杂区域具有相同的极性，并且第二掺杂区域的掺杂剂浓度高于第一掺杂区域的掺杂剂浓度。 第三掺杂区形成在第二阱中并位于第一和第二掺杂区之间。 第三和第一掺杂区域具有反向极性。 场板形成在第一和第二掺杂区域之间的表面区域上。

公开(公告)号：US20130277805A1

公开(公告)日：2013-10-24

申请号：US13450888

申请日：2012-04-19

申请人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

发明人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/6625 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/404 ,  H01L29/735

摘要： A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

摘要翻译： 半导体结构包括衬底，具有第一导电类型的第一阱，具有第二导电类型的第二阱，体区，第一掺杂区，第二掺杂区，第三掺杂区和场板。 在衬底中形成第一和第二阱。 身体区域形成在第二孔中。 第一和第二掺杂区分别形成在第一阱和体区中。 第二掺杂区域和第一掺杂区域具有相同的极性，并且第二掺杂区域的掺杂剂浓度高于第一掺杂区域的掺杂剂浓度。 第三掺杂区形成在第二阱中并位于第一和第二掺杂区之间。 第三和第一掺杂区域具有反向极性。 场板形成在第一和第二掺杂区域之间的表面区域上。

公开(公告)号：US08823128B2

公开(公告)日：2014-09-02

申请号：US13107405

申请日：2011-05-13

申请人： Wing-Chor Chan ,  Hsin-Liang Chen

发明人： Wing-Chor Chan ,  Hsin-Liang Chen

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L27/0635 ,  H01L27/0664

摘要： A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region.

摘要翻译： 提出了半导体结构。 在第一井和第二井之间形成第三井。 在第三阱的表面中形成第一掺杂区和第二掺杂区。 在第一掺杂区和第二掺杂区之间形成第三掺杂区。 在第一阱的表面中形成第四掺杂区域。 第五掺杂区形成在第二阱的表面中。 第一基区和第二基区分别形成在第一阱和第二阱的表面中。 第一肖特基势垒覆盖在第一基极区域和第一掺杂区域的一部分上。 第二肖特基势垒覆盖在第二基极区域和第二掺杂区域的一部分上。