公开(公告)号：US09461031B1

公开(公告)日：2016-10-04

申请号：US14939900

申请日：2015-11-12

申请人： Madhur Bobde

发明人： Madhur Bobde

IPC分类号： H01L29/66 ,  H01L27/02 ,  H01L29/74 ,  H01L29/866

CPC分类号： H01L27/0255 ,  H01L27/0744 ,  H01L27/075 ,  H01L27/0755 ,  H01L27/0761 ,  H01L29/0649 ,  H01L29/7416 ,  H01L29/861 ,  H01L29/866

摘要： A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

公开(公告)号：US4567501A

公开(公告)日：1986-01-28

申请号：US563887

申请日：1983-12-22

申请人： Takeshi Fukuda

发明人： Takeshi Fukuda

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/07 ,  H01L29/73 ,  H01L29/8605 ,  H01L27/04

CPC分类号： H01L27/0244 ,  H01L21/8226 ,  H01L27/075 ,  H01L29/7304 ,  H01L29/8605

摘要： An I.sup.2 L semiconductor device in which a p-type buried layer is formed on an n.sup.+ type silicon substrate by diffusion of boron, an epitaxial n-type layer is grown on the p-type buried layer, a p.sup.+ type region is formed in a ring shape to surround the epitaxial n-type layer with the bottom of the p.sup.+ region reaching to the p-type buried layer, an n-type resistor layer is formed in the epitaxial n-type layer by diffusion of phosphorus, and connections for electrodes are formed by diffusion of n.sup.+ type impurities in such a manner that the connections make contact with the resistor layer.

摘要翻译： 一种I2L半导体器件，其中通过硼的扩散在n +型硅衬底上形成p型掩埋层，在p型掩埋层上生长外延n型层，在p型掩模层中形成p +型区域 形状以围绕外延n型层，其中p +区的底部到达p型掩埋层，通过磷的扩散在外延n型层中形成n型电阻层，并且电极的连接为 通过使n +型杂质以连接方式与电阻层接触的方式形成。

公开(公告)号：US3919469A

公开(公告)日：1975-11-11

申请号：US33486873

申请日：1973-02-22

申请人： PHILIPS CORP

发明人： KASPERKOVITZ WOLFDIETRICH GEOR

IPC分类号： H01L27/07 ,  H01L27/102 ,  H01L27/105 ,  H01L27/146 ,  H04N5/335 ,  H04N3/16

CPC分类号： H01L27/1055 ,  H01L27/075 ,  H01L27/1023 ,  H01L27/14681 ,  H04N5/3577

摘要： A sensor including a pick-up panel having photosensitive transistors whose emitters are connected to column conductors and whose collectors are connected to row conductors. The row conductors are connected to emitters of row selection transistors whose bases are connected to outputs of a row scanning generator and whose interconnected collectors are connected to an output circuit. The column conductors are directly connected to a column scanning generator. The influence of parasitic capacitances is eliminated by causing the output circuit to provide a constant voltage, by always impressing voltage on the column conductors and by switching over the row selection transistors in a signal blanking period.

摘要翻译： 一种传感器，包括具有光敏晶体管的拾取面板，其发光体连接到列导体，并且其集电极连接到行导体。 行导体连接到行选择晶体管的发射极，其基极连接到行扫描发生器的输出端，并且其互连的集电极连接到输出电路。 列导体直接连接到列扫描发生器。 通过使输出电路提供恒定的电压，通过在列导体上施加电压并且在信号消隐期间切换行选择晶体管来消除寄生电容的影响。

公开(公告)号：US3769530A

公开(公告)日：1973-10-30

申请号：US3769530D

申请日：1971-02-24

申请人： NAT SEMICONDUCTOR CORP

发明人： KALB J ,  WIDLAR R

IPC分类号： H01L27/07 ,  H01L27/082 ,  H03K3/26

CPC分类号： H01L27/075 ,  H01L27/0821

摘要： A non-gold doped multiple emitter transistor device having an additional lateral PNP transistor formed in the collector region and a debiasing resistance formed in the base region, these elements cooperating to suppress the inherent PNP beta to substrate characteristic and control the inverse Hfe of the device. The emitter of the additional transistor is connected to the base of the MET through a pinch-type debiasing resistor formed in a projection of the base region of the MET, and the base and collector of the additional transistor are shorted together and connected to the collector of the MET so as to provide a shunt path around the base-collector junction thereof.

摘要翻译： 具有形成在集电极区域中的附加横向PNP晶体管的非金掺杂多发射体晶体管器件和在基极区域中形成的去偶电阻，这些元件协同作用以抑制固有的PNPβ至衬底特性并控制器件的反向Hfe 。 附加晶体管的发射极通过形成在MET的基极区域的突起中的夹紧型去噪电阻器连接到MET的基极，并且附加晶体管的基极和集电极被短路并连接到集电极 以提供围绕其基极 - 集电极结的分流路径。

公开(公告)号：US09006783B2

公开(公告)日：2015-04-14

申请号：US14296919

申请日：2014-06-05

申请人： International Business Machines Corporation

发明人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Chengwen Pei ,  Christopher S. Putnam ,  Theodorus E. Standaert

IPC分类号： H01L29/66 ,  H01L27/02

CPC分类号： H01L27/0262 ,  H01L21/84 ,  H01L27/0744 ,  H01L27/075 ,  H01L27/1203 ,  H01L29/66121 ,  H01L29/66181 ,  H01L29/66371 ,  H01L29/7408 ,  H01L29/87 ,  H01L29/945

摘要： Device structures and design structures that include a silicon controlled rectifier, as well as fabrication methods for such device structures. A well is formed in the device layer of a silicon-on-insulator substrate. A silicon controlled rectifier is formed that includes an anode in the well. A deep trench capacitor is formed that includes a plate coupled with the well. The plate of the deep trench capacitor extends from the device layer through a buried insulator layer of the silicon-on-insulator substrate and into a handle wafer of the silicon-on-insulator substrate.

摘要翻译： 包括可控硅整流器的器件结构和设计结构以及这种器件结构的制造方法。 在绝缘体上硅衬底的器件层中形成阱。 形成了可控整流器，其包括井中的阳极。 形成深沟槽电容器，其包括与该阱耦合的板。 深沟槽电容器的平板从器件层延伸穿过绝缘体上硅衬底的掩埋绝缘体层并进入绝缘体上硅衬底的处理晶片。

公开(公告)号：US20150001580A1

公开(公告)日：2015-01-01

申请号：US14296919

申请日：2014-06-05

申请人： International Business Machines Corporation

发明人： James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Chengwen Pei ,  Christopher S. Putnam ,  Theodorus E. Standaert

IPC分类号： H01L27/02

CPC分类号： H01L27/0262 ,  H01L21/84 ,  H01L27/0744 ,  H01L27/075 ,  H01L27/1203 ,  H01L29/66121 ,  H01L29/66181 ,  H01L29/66371 ,  H01L29/7408 ,  H01L29/87 ,  H01L29/945

摘要： Device structures and design structures that include a silicon controlled rectifier, as well as fabrication methods for such device structures. A well is formed in the device layer of a silicon-on-insulator substrate. A silicon controlled rectifier is formed that includes an anode in the well. A deep trench capacitor is formed that includes a plate coupled with the well. The plate of the deep trench capacitor extends from the device layer through a buried insulator layer of the silicon-on-insulator substrate and into a handle wafer of the silicon-on-insulator substrate.

摘要翻译： 包括可控硅整流器的器件结构和设计结构以及这种器件结构的制造方法。 在绝缘体上硅衬底的器件层中形成阱。 形成了可控整流器，其包括井中的阳极。 形成深沟槽电容器，其包括与该阱耦合的板。 深沟槽电容器的平板从器件层延伸穿过绝缘体上硅衬底的掩埋绝缘体层并进入绝缘体上硅衬底的处理晶片。

公开(公告)号：US20140363930A1

公开(公告)日：2014-12-11

申请号：US13913384

申请日：2013-06-08

申请人： Madhur Bobde

发明人： Madhur Bobde

IPC分类号： H01L29/866

CPC分类号： H01L27/0255 ,  H01L27/0744 ,  H01L27/075 ,  H01L27/0755 ,  H01L27/0761 ,  H01L29/0649 ,  H01L29/7416 ,  H01L29/861 ,  H01L29/866

摘要： A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

摘要翻译： 一种用于制造基本上遵循用于制造垂直半导体功率器件的制造工艺的瞬态电压抑制（TVS）阵列的方法。 该方法包括在半导体衬底中打开第一导电类型的外延层中的多个隔离沟槽的步骤，然后施加用于在两个隔离沟槽之间掺杂具有第二导电类型的体区的体掩模。 该方法还包括施加用于注入构成多个二极管的第一导电类型的多个掺杂区域的源极掩模的步骤，其中隔离沟槽由于掺杂区域之间的闩锁而隔离和防止寄生PNP或NPN晶体管 的不同导电类型。

公开(公告)号：US08841174B1

公开(公告)日：2014-09-23

申请号：US13932132

申请日：2013-07-01

申请人： International Business Machines Corporation

发明人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Chengwen Pei ,  Christopher S. Putnam ,  Theodorus E. Standaert

IPC分类号： H01L21/332 ,  H01L29/74 ,  H01L29/66

CPC分类号： H01L27/0262 ,  H01L21/84 ,  H01L27/0744 ,  H01L27/075 ,  H01L27/1203 ,  H01L29/66121 ,  H01L29/66181 ,  H01L29/66371 ,  H01L29/7408 ,  H01L29/87 ,  H01L29/945

摘要： Device structures and design structures that include a silicon controlled rectifier, as well as fabrication methods for such device structures. A well is formed in the device layer of a silicon-on-insulator substrate. A silicon controlled rectifier is formed that includes an anode in the well. A deep trench capacitor is formed that includes a plate coupled with the well. The plate of the deep trench capacitor extends from the device layer through a buried insulator layer of the silicon-on-insulator substrate and into a handle wafer of the silicon-on-insulator substrate.

摘要翻译： 包括可控硅整流器的器件结构和设计结构以及这种器件结构的制造方法。 在绝缘体上硅衬底的器件层中形成阱。 形成了可控整流器，其包括井中的阳极。 形成深沟槽电容器，其包括与该阱耦合的板。 深沟槽电容器的平板从器件层延伸穿过绝缘体上硅衬底的掩埋绝缘体层并进入绝缘体上硅衬底的处理晶片。

公开(公告)号：US08737124B2

公开(公告)日：2014-05-27

申请号：US13457262

申请日：2012-04-26

申请人： Shuichi Tsukada ,  Yasuhiro Uchiyama

发明人： Shuichi Tsukada ,  Yasuhiro Uchiyama

IPC分类号： G11C11/24 ,  H01L27/06 ,  H01L27/102 ,  G11C11/39 ,  H01L49/02 ,  H01L29/78

CPC分类号： G11C11/39 ,  G11C11/40 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/411 ,  H01L27/075 ,  H01L27/1021 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L28/91 ,  H01L29/7841

摘要： There is provided a semiconductor device including a word line, a bit line, a power supply node, a memory element, and a capacitor. The memory element includes at least first and second regions that form a PN junction between the bit line and the power supply node, and a third region that forms a PN junction with the second region. The capacitor includes a first electrode provided independently from the second region of the memory element and electrically connected to the second region of the memory element, and a second electrode connected to the word line.

摘要翻译： 提供了包括字线，位线，电源节点，存储元件和电容器的半导体器件。 存储器元件至少包括在位线和电源节点之间形成PN结的第一和第二区域，以及与第二区域形成PN结的第三区域。 电容器包括独立于存储元件的第二区域设置并电连接到存储元件的第二区域的第一电极和连接到字线的第二电极。

公开(公告)号：US06642605B2

公开(公告)日：2003-11-04

申请号：US10162244

申请日：2002-06-04

申请人： Tomotaka Fujisawa ,  Chihiro Arai

发明人： Tomotaka Fujisawa ,  Chihiro Arai

IPC分类号： H01L2900

CPC分类号： H01L27/075 ,  H01L27/0761

摘要： In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

摘要翻译： 在具有使用双极型晶体管的结型二极管的半导体器件及其制造方法中，提高了二极管电流与漏电流的比例，并且在不增加处理的情况下提高了闭锁电阻。 形成p型半导体衬底，集电极掩埋区和n型外延层，在n型外延层中形成ap型第一杂质区，在第一杂质区形成n型第二杂质区， +>沉降片，并且形成集电极，在第一和第二杂质区上形成有公共电极。