公开(公告)号：US20110057243A1

公开(公告)日：2011-03-10

申请号：US12943945

申请日：2010-11-11

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L27/12

CPC分类号： H01L27/115

摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.

摘要翻译： 设置在SOI衬底中的非易失性存储器。 非易失性存储器包括存储单元和第一导电类型掺杂区域。 存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。 栅极设置在SOI衬底上。 电荷存储结构设置在栅极和SOI衬底之间。 底部电介质层设置在电荷存储层和SOI衬底之间。 第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。 第一导电型掺杂区域设置在第一导电型硅体层中，并且与栅极下方的第一导电型硅体层电连接。

公开(公告)号：US20070045716A1

公开(公告)日：2007-03-01

申请号：US11163716

申请日：2005-10-28

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L29/792 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/115

摘要： A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.

摘要翻译： 公开了包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一栅极结构和第二栅极结构的非易失性存储器。 掺杂区域设置在衬底中，第二掺杂区域设置在第一掺杂区域和第三掺杂区域之间。 第一栅极结构设置在第一掺杂区和第二掺杂区之间的衬底上。 第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的衬底上，并且包括隧道电介质层，电荷捕获结构和从下向上的栅极。

公开(公告)号：US07855417B2

公开(公告)日：2010-12-21

申请号：US11833235

申请日：2007-08-03

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L29/786 ,  H01L29/792

CPC分类号： H01L27/115

摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.

摘要翻译： 设置在SOI衬底中的非易失性存储器。 非易失性存储器包括存储单元和第一导电类型掺杂区域。 存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。 栅极设置在SOI衬底上。 电荷存储结构设置在栅极和SOI衬底之间。 底部电介质层设置在电荷存储层和SOI衬底之间。 第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。 第一导电型掺杂区域设置在第一导电型硅体层中，并且电连接到栅极下方的导电型硅体层。

公开(公告)号：US20080031038A1

公开(公告)日：2008-02-07

申请号：US11833235

申请日：2007-08-03

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C11/34 ,  H01L29/792

CPC分类号： H01L27/115

摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.

摘要翻译： 设置在SOI衬底中的非易失性存储器。 非易失性存储器包括存储单元和第一导电类型掺杂区域。 存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。 栅极设置在SOI衬底上。 电荷存储结构设置在栅极和SOI衬底之间。 底部电介质层设置在电荷存储层和SOI衬底之间。 第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。 第一导电型掺杂区域设置在第一导电型硅体层中，并且与栅极下方的第一导电型硅体层电连接。

公开(公告)号：US06922363B2

公开(公告)日：2005-07-26

申请号：US10707564

申请日：2003-12-22

申请人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

发明人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475

摘要： A method for writing a memory module includes providing a plurality of memory cells. Each memory cell includes a substrate, a P-type drain and source, a gate, and a stack dielectric layer which stores 2-bit data. Memory cells are arranged in a matrix with gates and sources on the same row connected respectively to the same word line and same source line, and drains on the same column connected to the same bit line. Each line receives a respective voltage with the word line of the memory cell to be written receiving voltage to turn on its P-type channel, the word line of the memory cell not to be written receiving voltage to turn off its P-type channel, and the bit line of the memory cell to be written receiving voltage so that a hot hole in its P-type channel induces hot electron injection into its stack dielectric layer.

摘要翻译： 一种用于写存储器模块的方法包括提供多个存储器单元。 每个存储单元包括存储2位数据的衬底，P型漏极和源极，栅极和堆叠电介质层。 存储单元被布置在矩阵中，同一行上的栅极和源极分别连接到相同的字线和相同的源极线，并且在连接到同一位线的同一列上的漏极。 每行接收与存储单元的字线相对应的电压以写入接收电压以接通其P型通道，存储单元的字线不被写入接收电压以关闭其P型通道， 并且要写入的存储单元的位线接收电压，使得其P型沟道中的热孔将热电子注入其堆叠电介质层。

公开(公告)号：US20050030793A1

公开(公告)日：2005-02-10

申请号：US10707564

申请日：2003-12-22

申请人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

发明人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475

摘要： A method for writing a memory module includes providing a plurality of memory cells. Each memory cell includes a substrate, a P-type drain and source, a gate, and a stack dielectric layer which stores 2-bit data. Memory cells are arranged in a matrix with gates and sources on the same row connected respectively to the same word line and same source line, and drains on the same column connected to the same bit line. Each line receives a respective voltage with the word line of the memory cell to be written receiving voltage to turn on its P-type channel, the word line of the memory cell not to be written receiving voltage to turn off its P-type channel, and the bit line of the memory cell to be written receiving voltage so that a hot hole in its P-type channel induces hot electron injection into its stack dielectric layer.

摘要翻译： 一种用于写存储器模块的方法包括提供多个存储器单元。 每个存储单元包括存储2位数据的衬底，P型漏极和源极，栅极和堆叠电介质层。 存储单元被布置在矩阵中，同一行上的栅极和源极分别连接到相同的字线和相同的源极线，并且在连接到同一位线的同一列上的漏极。 每行接收与存储单元的字线相对应的电压以写入接收电压以接通其P型通道，存储单元的字线不被写入接收电压以关闭其P型通道， 并且要写入的存储单元的位线接收电压，使得其P型沟道中的热孔将热电子注入其堆叠电介质层。

公开(公告)号：US07903472B2

公开(公告)日：2011-03-08

申请号：US12565778

申请日：2009-09-24

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C11/34

CPC分类号： H01L27/115

摘要： An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.

摘要翻译： 提供了适用于设置在包括第一导电型硅体层的SOI衬底上的非易失性存储器的非易失性存储器的操作方法。 非易失性存储器包括栅极，电荷存储结构，第二导电类型漏极区域和第二导电型源极区域。 在操作这种非易失性存储器时，电压施加到门下方的栅极，第二导电型漏极区域，第二导电型源极区域和第一导电型硅体层，以将电荷或空穴注入电荷 通过选自由通道热载流子注入，源侧注入，带对带隧穿热载流子注入和Fowler-Nordheim（FN）隧道的组中选择的方法，从电荷存储结构排出电子。

公开(公告)号：US20050098817A1

公开(公告)日：2005-05-12

申请号：US10707700

申请日：2004-01-05

申请人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

发明人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792 ,  H01L29/24

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L29/7923

摘要： A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.

摘要翻译： 存储单元包括N型阱，三个P型掺杂区，第一层叠电介质层，第一栅极，第二堆叠电介质层和第二栅极。 在N阱上形成三个P型掺杂区域。 在三个P型掺杂区域中，第一电介质叠层形成在N型阱上，并且在第一掺杂区和第二掺杂区之间。 第一栅极形成在第一堆叠电介质层上。 在三个P型掺杂区域中，第二层叠电介质层形成在N型阱上，并且在第二掺杂区域和第三掺杂区域之间。 第二栅极形成在第二堆叠电介质层上。

公开(公告)号：US20100014359A1

公开(公告)日：2010-01-21

申请号：US12565778

申请日：2009-09-24

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L27/115

摘要： An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.

摘要翻译： 提供了适用于设置在包括第一导电型硅体层的SOI衬底上的非易失性存储器的非易失性存储器的操作方法。 非易失性存储器包括栅极，电荷存储结构，第二导电类型漏极区域和第二导电型源极区域。 在操作这种非易失性存储器时，电压施加到门下方的栅极，第二导电型漏极区域，第二导电型源极区域和第一导电型硅体层，以将电荷或空穴注入电荷 通过选自由通道热载流子注入，源侧注入，带对带隧穿热载流子注入和Fowler-Nordheim（FN）隧道的组中选择的方法，从电荷存储结构排出电子。

公开(公告)号：US07262457B2

公开(公告)日：2007-08-28

申请号：US10905056

申请日：2004-12-13

申请人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

发明人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

IPC分类号： H01L29/788

CPC分类号： G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/7923

摘要： A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.

摘要翻译： 存储单元包括N型阱，三个P型掺杂区，第一层叠电介质层，第一栅极，第二堆叠电介质层和第二栅极。 在N阱上形成三个P型掺杂区域。 在三个P型掺杂区域中，第一电介质叠层形成在N型阱上，并且在第一掺杂区和第二掺杂区之间。 第一栅极形成在第一堆叠电介质层上。 在三个P型掺杂区域中，第二层叠电介质层形成在N型阱上，并且在第二掺杂区域和第三掺杂区域之间。 第二栅极形成在第二堆叠电介质层上。