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    Double patterning technology using single-patterning-spacer-technique
    1.
    发明授权
    Double patterning technology using single-patterning-spacer-technique 有权
    使用单图案化间隔技术的双重图案化技术

    公开(公告)号：US08211807B2

    公开(公告)日：2012-07-03

    申请号：US12907640

    申请日：2010-10-19

    申请人： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

    发明人： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC分类号： H01L21/461 ,  H01L21/302

    CPC分类号： H01L21/0337

    摘要： A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.

    摘要翻译： 形成集成电路结构的方法包括形成平行于第一方向和晶片表示的第一和第二多个轨道。 以交替模式分配第一和第二多个轨道。 第一多个图案布置在第一多个轨道上，而不是在第二多个轨道上。 第二多个图案布置在第二多个轨道上而不是在第一多个轨道上。 第一多个图案在垂直于第一方向的第一方向和第二方向上延伸，使得第二多个图案中的每一个被第一多个图案的部分包围，并且基本上没有相邻的图案 晶片表面上的第一多个图案具有大于预定间距的间隔。

    Double Patterning Technology Using Single-Patterning-Spacer-Technique
    2.
    发明申请
    Double Patterning Technology Using Single-Patterning-Spacer-Technique 有权
    使用单模式间隔技术的双重图案化技术

    公开(公告)号：US20120091592A1

    公开(公告)日：2012-04-19

    申请号：US12907640

    申请日：2010-10-19

    申请人： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

    发明人： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC分类号： H01L29/41 ,  H01L21/283 ,  G06F17/50 ,  G03F7/20 ,  G03F1/00

    CPC分类号： H01L21/0337

    摘要： A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.

    摘要翻译： 形成集成电路结构的方法包括形成平行于第一方向和晶片表示的第一和第二多个轨道。 以交替模式分配第一和第二多个轨道。 第一多个图案布置在第一多个轨道上，而不是在第二多个轨道上。 第二多个图案布置在第二多个轨道上而不是在第一多个轨道上。 第一多个图案在垂直于第一方向的第一方向和第二方向上延伸，使得第二多个图案中的每一个被第一多个图案的部分包围，并且基本上没有相邻的图案 晶片表面上的第一多个图案具有大于预定间距的间隔。

    METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT
    3.
    发明申请
    METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT 有权
    实现多种图案技术的方法和装置合规设计布局

    公开(公告)号：US20120131528A1

    公开(公告)日：2012-05-24

    申请号：US12953661

    申请日：2010-11-24

    申请人： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

    发明人： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G03F7/70433 ,  G03F7/70466

    摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.

    摘要翻译： 提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。 示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。 如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。 如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有 彩色图案布局的特点。 每个面具都包含单一颜色的特征。

    Method and apparatus for achieving multiple patterning technology compliant design layout
    4.
    发明授权
    Method and apparatus for achieving multiple patterning technology compliant design layout 有权
    用于实现多种图案化技术兼容的设计布局的方法和装置

    公开(公告)号：US08418111B2

    公开(公告)日：2013-04-09

    申请号：US12953661

    申请日：2010-11-24

    申请人： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

    发明人： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G03F7/70433 ,  G03F7/70466

    摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.

    摘要翻译： 提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。 示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。 如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。 如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有 彩色图案布局的特点。 每个面具都包含单一颜色的特征。

    Semiconductor Device With Self-Aligned Interconnects and Blocking Portions
    5.
    发明申请
    Semiconductor Device With Self-Aligned Interconnects and Blocking Portions 有权
    具有自对准互连和阻塞部分的半导体器件

    公开(公告)号：US20130285246A1

    公开(公告)日：2013-10-31

    申请号：US13458396

    申请日：2012-04-27

    申请人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

    发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

    摘要翻译： 公开了一种用于制造装置的装置和方法。 示例性器件包括设置在衬底上的第一导电层，第一导电层包括沿第一方向延伸的第一多个导电线。 该装置还包括设置在第一导电层上的第二导电层，第二导电层包括沿第二方向延伸的第二多个导电线。 该装置还包括形成在第一多个导线的第一导线与第二多个导线的第一导线电接触的界面处的自对准互连。 该装置还包括插入在第一多个导线中的第二导线与第二多个导线之间的第二导线之间的阻挡部分。

    Semiconductor device with self-aligned interconnects and blocking portions
    6.
    发明授权
    Semiconductor device with self-aligned interconnects and blocking portions 有权
    具有自对准互连和阻塞部分的半导体器件

    公开(公告)号：US08907497B2

    公开(公告)日：2014-12-09

    申请号：US13458396

    申请日：2012-04-27

    申请人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

    发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

    摘要翻译： 公开了一种用于制造装置的装置和方法。 示例性器件包括设置在衬底上的第一导电层，第一导电层包括沿第一方向延伸的第一多个导电线。 该装置还包括设置在第一导电层上的第二导电层，第二导电层包括沿第二方向延伸的第二多个导电线。 该装置还包括形成在第一多个导线的第一导线与第二多个导线的第一导线电接触的界面处的自对准互连。 该装置还包括插入在第一多个导线中的第二导线与第二多个导线之间的第二导线之间的阻挡部分。

    Semiconductor Device with Self-Aligned Interconnects
    8.
    发明申请
    Semiconductor Device with Self-Aligned Interconnects 有权
    具有自对准互连的半导体器件

    公开(公告)号：US20130270704A1

    公开(公告)日：2013-10-17

    申请号：US13444648

    申请日：2012-04-11

    申请人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

    发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

    IPC分类号： H01L23/482 ,  H01L21/768

    CPC分类号： H01L23/522 ,  H01L21/31144 ,  H01L21/76816 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.

    摘要翻译： 公开了一种用于制造多层器件的多层器件和方法。 示例性的多层器件包括衬底，设置在衬底上的第一层间电介质层（ILD）层，以及包括形成在第一ILD层中的第一多个导电线的第一导电层。 该装置还包括设置在第一ILD层上的第二ILD层和包括形成在第二ILD层中的第二多个导电线的第二导电层。 所述第二多个导电线中的至少一个导电线邻近所述第一多个导线的至少一个导电线形成。 第二多个导电线中的至少一个导线在接口处接触第一多个导线的至少一个导电线。

    Interconnect structure having smaller transition layer via
    9.
    发明授权
    Interconnect structure having smaller transition layer via 有权
    互连结构具有较小的过渡层通孔

    公开(公告)号：US09553043B2

    公开(公告)日：2017-01-24

    申请号：US13438565

    申请日：2012-04-03

    申请人： Lee-Chung Lu ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Fang-Yu Fan ,  Yu-Hsiang Kao ,  Dian-Hau Chen ,  Shyue-Shyh Lin ,  Chii-Ping Chen

    发明人： Lee-Chung Lu ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Fang-Yu Fan ,  Yu-Hsiang Kao ,  Dian-Hau Chen ,  Shyue-Shyh Lin ,  Chii-Ping Chen

    IPC分类号： H01L23/522 ,  H01L23/528

    CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

    摘要翻译： 一种互连结构，其包括在衬底上的底层，其中底层包括至少一个底层线和至少一个底层通孔。 互连结构还包括在底层上的过渡层，其中过渡层包括至少一个过渡层线和至少一个过渡层通孔。 互连结构还包括过渡层上的顶层，其中顶层包括至少一个顶层线和至少一个顶层通孔。 所述至少一个过渡层通孔具有比所述至少一个顶层通孔的横截面面积小至少30％的横截面面积。