公开(公告)号：US08418111B2

公开(公告)日：2013-04-09

申请号：US12953661

申请日：2010-11-24

申请人： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

发明人： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G03F7/70433 ,  G03F7/70466

摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.

摘要翻译： 提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。 示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。 如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。 如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有 彩色图案布局的特点。 每个面具都包含单一颜色的特征。

公开(公告)号：US20120131528A1

公开(公告)日：2012-05-24

申请号：US12953661

申请日：2010-11-24

申请人： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

发明人： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G03F7/70433 ,  G03F7/70466

摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.

摘要翻译： 提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。 示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。 如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。 如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有 彩色图案布局的特点。 每个面具都包含单一颜色的特征。

公开(公告)号：US20120091592A1

公开(公告)日：2012-04-19

申请号：US12907640

申请日：2010-10-19

申请人： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： H01L29/41 ,  H01L21/283 ,  G06F17/50 ,  G03F7/20 ,  G03F1/00

CPC分类号： H01L21/0337

摘要： A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.

摘要翻译： 形成集成电路结构的方法包括形成平行于第一方向和晶片表示的第一和第二多个轨道。 以交替模式分配第一和第二多个轨道。 第一多个图案布置在第一多个轨道上，而不是在第二多个轨道上。 第二多个图案布置在第二多个轨道上而不是在第一多个轨道上。 第一多个图案在垂直于第一方向的第一方向和第二方向上延伸，使得第二多个图案中的每一个被第一多个图案的部分包围，并且基本上没有相邻的图案 晶片表面上的第一多个图案具有大于预定间距的间隔。

公开(公告)号：US08211807B2

公开(公告)日：2012-07-03

申请号：US12907640

申请日：2010-10-19

申请人： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/0337

摘要： A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.

摘要翻译： 形成集成电路结构的方法包括形成平行于第一方向和晶片表示的第一和第二多个轨道。 以交替模式分配第一和第二多个轨道。 第一多个图案布置在第一多个轨道上，而不是在第二多个轨道上。 第二多个图案布置在第二多个轨道上而不是在第一多个轨道上。 第一多个图案在垂直于第一方向的第一方向和第二方向上延伸，使得第二多个图案中的每一个被第一多个图案的部分包围，并且基本上没有相邻的图案 晶片表面上的第一多个图案具有大于预定间距的间隔。

公开(公告)号：US20120167021A1

公开(公告)日：2012-06-28

申请号：US13084255

申请日：2011-04-11

申请人： Huang-Yu Chen ,  Yuan-Te Hou ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Huang-Yu Chen ,  Yuan-Te Hou ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70466

摘要： A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell.

摘要翻译： 提供了一种用于提供用于多个图案化技术的单元布局的系统和方法。 要被图案化的区域被分成对应于各种掩模的交替位置。 在布局过程中，沿着单元边界定位的站点被限制为具有与边界站点相关联的掩码中的模式。 当放置时，各个单元被布置成使得相邻的单元交替分配给各种掩模的位置。 以这种方式，设计者知道在设计每个单独的单元时，一个单元的掩模图案将太靠近相邻单元的掩模图案。

公开(公告)号：US08584052B2

公开(公告)日：2013-11-12

申请号：US13084255

申请日：2011-04-11

申请人： Huang-Yu Chen ,  Yuan-Te Hou ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Huang-Yu Chen ,  Yuan-Te Hou ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70466

摘要： A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell.

摘要翻译： 提供了一种用于提供用于多个图案化技术的单元布局的系统和方法。 要被图案化的区域被分成对应于各种掩模的交替位置。 在布局过程中，沿着单元边界定位的站点被限制为具有与边界站点相关联的掩码中的模式。 当放置时，各个单元被布置成使得相邻的单元交替分配给各种掩模的位置。 以这种方式，设计者知道在设计每个单独的单元时，一个单元的掩模图案将太靠近相邻单元的掩模图案。

公开(公告)号：US08365102B2

公开(公告)日：2013-01-29

申请号：US12788789

申请日：2010-05-27

申请人： Dio Wang ,  Ken-Hsien Hsieh ,  Huang-Yu Chen ,  Li-Chun Tien ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Dio Wang ,  Ken-Hsien Hsieh ,  Huang-Yu Chen ,  Li-Chun Tien ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F17/5077 ,  G06F2217/12 ,  G21K5/00

摘要： A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout.

摘要翻译： 一种方法和系统检查双重图案化布局，并输出G0规则违规和关键G0空格的表示。 该方法包括接收具有图案的布局数据，确定相邻图案元素之间的每个距离是否是G0空间，找到形成G0规则违例的所有G0空间，找到作为关键G0空间的所有G0空间，并输出 将G0规则违规和关键G0空格表示为输出设备。 通过解决G0规则违规和关键G0空间，设计检查器可以有效地生成符合双图案技术（DPT）的布局。

公开(公告)号：US20130285246A1

公开(公告)日：2013-10-31

申请号：US13458396

申请日：2012-04-27

申请人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

摘要翻译： 公开了一种用于制造装置的装置和方法。 示例性器件包括设置在衬底上的第一导电层，第一导电层包括沿第一方向延伸的第一多个导电线。 该装置还包括设置在第一导电层上的第二导电层，第二导电层包括沿第二方向延伸的第二多个导电线。 该装置还包括形成在第一多个导线的第一导线与第二多个导线的第一导线电接触的界面处的自对准互连。 该装置还包括插入在第一多个导线中的第二导线与第二多个导线之间的第二导线之间的阻挡部分。

公开(公告)号：US08907497B2

公开(公告)日：2014-12-09

申请号：US13458396

申请日：2012-04-27

申请人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

摘要翻译： 公开了一种用于制造装置的装置和方法。 示例性器件包括设置在衬底上的第一导电层，第一导电层包括沿第一方向延伸的第一多个导电线。 该装置还包括设置在第一导电层上的第二导电层，第二导电层包括沿第二方向延伸的第二多个导电线。 该装置还包括形成在第一多个导线的第一导线与第二多个导线的第一导线电接触的界面处的自对准互连。 该装置还包括插入在第一多个导线中的第二导线与第二多个导线之间的第二导线之间的阻挡部分。

公开(公告)号：US09627310B2

公开(公告)日：2017-04-18

申请号：US13444648

申请日：2012-04-11

申请人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532

CPC分类号： H01L23/522 ,  H01L21/31144 ,  H01L21/76816 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.