公开(公告)号：US20200162294A1

公开(公告)日：2020-05-21

申请号：US16750200

申请日：2020-01-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Mingjun Fan ,  Jianhua Zheng ,  Daiping Tang

IPC: H04L27/148 ,  H04L25/03 ,  H04B1/10

Abstract: This application discloses a communications chip structure, including: a channel selection module, configured to receive an input signal, where the input signal is a signal of a preset narrow bandwidth span or a signal of a preset wide bandwidth span; and a digital baseband module, configured to control the channel selection module to select a first sampling and quantification channel when the input signal is a signal of the preset narrow bandwidth span, or control the channel selection module to select a second sampling and quantification channel when the input signal is a signal of the preset wide bandwidth span. The channel selection module is further configured to send the input signal to the first sampling and quantification channel or the second sampling and quantification channel for sampling and quantification.

公开(公告)号：US20150214970A1

公开(公告)日：2015-07-30

申请号：US14607282

申请日：2015-01-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingjun Fan ,  Liming Fang ,  Yuan Liu

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/00 ,  H03M1/0602 ,  H03M1/365 ,  H03M7/165

Abstract: The present invention relates to an analog to digital converter. The analog to digital converter includes comparing modules at multi levels, where a comparing module at each level includes a comparator and a metastable state determining unit. The comparator is configured to, when a previous-level comparing module is not in a metastable state, receive a first clock, a first input signal, and a second input signal, and compare the first input signal with the second input signal. The metastable state determining unit is configured to, when the previous-level comparing module is not in a metastable state, receive the first clock, generate a reference clock according to the first clock, and if a second clock that is output by the comparator is later than the reference clock, determine that the current-level comparing module is in a metastable state.

Abstract translation: 本发明涉及一种模数转换器。 模数转换器包括在多级别比较模块，其中每个级别的比较模块包括比较器和亚稳态确定单元。 比较器被配置为当前一级比较模块不处于亚稳状态时，接收第一时钟，第一输入信号和第二输入信号，并将第一输入信号与第二输入信号进行比较。 亚稳态确定单元被配置为当前级电平比较模块不处于亚稳态时，接收第一时钟，根据第一时钟生成参考时钟，并且如果由比较器输出的第二时钟是 晚于参考时钟，确定当前级别的比较模块处于亚稳状态。

公开(公告)号：US10904054B2

公开(公告)日：2021-01-26

申请号：US16750200

申请日：2020-01-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Mingjun Fan ,  Jianhua Zheng ,  Daiping Tang

IPC: H04L27/148 ,  H04B1/10 ,  H04L25/03

Abstract: This application discloses a communications chip structure, including: a channel selection module, configured to receive an input signal, where the input signal is a signal of a preset narrow bandwidth span or a signal of a preset wide bandwidth span; and a digital baseband module, configured to control the channel selection module to select a first sampling and quantification channel when the input signal is a signal of the preset narrow bandwidth span, or control the channel selection module to select a second sampling and quantification channel when the input signal is a signal of the preset wide bandwidth span. The channel selection module is further configured to send the input signal to the first sampling and quantification channel or the second sampling and quantification channel for sampling and quantification.

公开(公告)号：US09106248B1

公开(公告)日：2015-08-11

申请号：US14607282

申请日：2015-01-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingjun Fan ,  Liming Fang ,  Yuan Liu

IPC: H03M1/34 ,  H03M1/12 ,  H03M7/16 ,  H03M1/00 ,  H03M1/36

CPC classification number: H03M1/12 ,  H03M1/00 ,  H03M1/0602 ,  H03M1/365 ,  H03M7/165

Abstract: The present invention relates to an analog to digital converter. The analog to digital converter includes comparing modules at multi levels, where a comparing module at each level includes a comparator and a metastable state determining unit. The comparator is configured to, when a previous-level comparing module is not in a metastable state, receive a first clock, a first input signal, and a second input signal, and compare the first input signal with the second input signal. The metastable state determining unit is configured to, when the previous-level comparing module is not in a metastable state, receive the first clock, generate a reference clock according to the first clock, and if a second clock that is output by the comparator is later than the reference clock, determine that the current-level comparing module is in a metastable state.

Abstract translation: 本发明涉及一种模数转换器。 模数转换器包括在多级别比较模块，其中每个级别的比较模块包括比较器和亚稳态确定单元。 比较器被配置为当前一级比较模块不处于亚稳状态时，接收第一时钟，第一输入信号和第二输入信号，并将第一输入信号与第二输入信号进行比较。 亚稳态确定单元被配置为当前级电平比较模块不处于亚稳态时，接收第一时钟，根据第一时钟生成参考时钟，并且如果由比较器输出的第二时钟是 晚于参考时钟，确定当前级别的比较模块处于亚稳状态。