公开(公告)号：US20180267482A1

公开(公告)日：2018-09-20

申请号：US15985252

申请日：2018-05-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ying WU ,  Robert Bogdan STASZEWSKI ,  Yihong MAO

IPC: G04F10/00 ,  H03M3/00

CPC classification number: G04F10/005 ,  H03M3/414

Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

公开(公告)号：US20170329284A1

公开(公告)日：2017-11-16

申请号：US15667114

申请日：2017-08-02

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ying WU ,  Robert Bogdan STASZEWSKI ,  Yihong MAO

IPC: G04F10/00

CPC classification number: G04F10/005 ,  H03M3/414

Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

公开(公告)号：US20170322520A1

公开(公告)日：2017-11-09

申请号：US15660514

申请日：2017-07-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ying WU ,  Robert Bogdan STASZEWSKI ,  Yihong MAO

IPC: G04F10/00 ,  H03M1/50 ,  H03K5/135

CPC classification number: G04F10/005 ,  H03H19/004 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/50 ,  H03M2201/4233

Abstract: A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.