SYSTEM AND METHOD FOR REDUCING LAYOUT-DEPENDENT EFFECTS
    1.
    发明申请
    SYSTEM AND METHOD FOR REDUCING LAYOUT-DEPENDENT EFFECTS 有权
    减少排列依赖效应的系统和方法

    公开(公告)号:US20130290916A1

    公开(公告)日:2013-10-31

    申请号:US13459288

    申请日:2012-04-30

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5036 G06F17/5081

    摘要: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

    摘要翻译: 一种方法包括从半导体电路的第一布局提取第一网表并基于第一网表估计与布局有关的效果数据。 基于使用电子设计自动化工具的第一网表执行半导体电路的第一仿真,并且基于使用电子设计自动化工具的电路示意图来执行半导体电路的第二仿真。 计算至少一个与布局相关的效果的重量和灵敏度,并且基于重量和灵敏度来调整半导体电路的第一布局以提供半导体电路的第二布局。 第二布局存储在非瞬态存储介质中。

    SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT RC EXTRACTION NETLIST
    2.
    发明申请
    SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT RC EXTRACTION NETLIST 有权
    用于创建频率依赖性RC提取网络列表的系统和方法

    公开(公告)号:US20120254811A1

    公开(公告)日:2012-10-04

    申请号:US13076649

    申请日:2011-03-31

    IPC分类号: G06F17/50

    摘要: A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.

    摘要翻译: 一种方法包括使用频率相关电路近似半导体衬底的物理特性,并且基于频率相关电路创建用于半导体衬底的技术文件。 通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。 技术文件适用于电子设计自动化工具,用于创建半导体衬底的网表,并存储在非瞬态计算机可读存储介质中。

    METHOD OF CIRCUIT DESIGN YIELD ANALYSIS
    4.
    发明申请
    METHOD OF CIRCUIT DESIGN YIELD ANALYSIS 有权
    电路设计分析方法

    公开(公告)号:US20130246986A1

    公开(公告)日:2013-09-19

    申请号:US13535709

    申请日:2012-06-28

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5036 G06F2217/10

    摘要: A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.

    摘要翻译: 一种方法包括(a)产生一组样本,每个样本表示相应的一组半导体制造工艺变化值; (b)基于与每个样本相对应的半导体制造工艺变化值的集合的概率来选择该组样本的第一子集; (c)在不执行蒙特卡罗模拟的情况下,基于所述一组样本和所述第一子集的相对大小来估计半导体产品的屈服度量; 以及(d)如果估计的收益率测量低于规格收益率值,则输出设计修改适当的指示。