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    SYSTEM AND METHOD FOR REDUCING LAYOUT-DEPENDENT EFFECTS
    2.
    发明申请
    SYSTEM AND METHOD FOR REDUCING LAYOUT-DEPENDENT EFFECTS 有权
    减少排列依赖效应的系统和方法

    公开(公告)号：US20130290916A1

    公开(公告)日：2013-10-31

    申请号：US13459288

    申请日：2012-04-30

    申请人： Hui Yu LEE ,  Feng Wei KUO ,  Ching-Shun YANG ,  Yi-Kan CHENG ,  Jui-Feng KUAN

    发明人： Hui Yu LEE ,  Feng Wei KUO ,  Ching-Shun YANG ,  Yi-Kan CHENG ,  Jui-Feng KUAN

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5081

    摘要： A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

    摘要翻译： 一种方法包括从半导体电路的第一布局提取第一网表并基于第一网表估计与布局有关的效果数据。 基于使用电子设计自动化工具的第一网表执行半导体电路的第一仿真，并且基于使用电子设计自动化工具的电路示意图来执行半导体电路的第二仿真。 计算至少一个与布局相关的效果的重量和灵敏度，并且基于重量和灵敏度来调整半导体电路的第一布局以提供半导体电路的第二布局。 第二布局存储在非瞬态存储介质中。

    LOCK DETECTOR AND METHOD OF DETECTING LOCK STATUS FOR PHASE LOCK LOOP
    3.
    发明申请
    LOCK DETECTOR AND METHOD OF DETECTING LOCK STATUS FOR PHASE LOCK LOOP 有权
    锁定检测器和检测锁相状态的方法

    公开(公告)号：US20130120035A1

    公开(公告)日：2013-05-16

    申请号：US13297658

    申请日：2011-11-16

    申请人： Feng Wei KUO ,  Kyle YEN ,  Huan-Neng CHEN ,  Yen-Jen CHEN ,  Chewn-Pu JOU

    发明人： Feng Wei KUO ,  Kyle YEN ,  Huan-Neng CHEN ,  Yen-Jen CHEN ,  Chewn-Pu JOU

    IPC分类号： H03L7/08

    CPC分类号： H03L7/095

    摘要： A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.

    摘要翻译： 用于PLL电路的锁定检测器包括第一信号计数电路，第二信号计数电路，比较器和锁定状态单元。 第一信号计数电路被配置为根据第一振荡信号和预定周期值来定义多个观察周期。 第二信号计数电路被配置为根据每个观测周期内的第二振荡信号来确定最大计数器值，并且相对于第一振荡信号产生第二振荡信号。 比较器被配置为为每个观察周期确定最大计数器值是否等于预定周期值。 锁定状态单元被配置为基于最大计数器值等于预定数量的连续观察周期中的预定周期值的锁定信号。

    SYSTEM AND METHOD FOR RC CALIBRATION USING PHASE AND FREQUENCY
    4.
    发明申请
    SYSTEM AND METHOD FOR RC CALIBRATION USING PHASE AND FREQUENCY 有权
    使用相位和频率进行RC校准的系统和方法

    公开(公告)号：US20110279175A1

    公开(公告)日：2011-11-17

    申请号：US12777293

    申请日：2010-05-11

    申请人： Feng Wei KUO ,  Tsung-Hsien TSAI ,  Jia-Liang CHEN

    发明人： Feng Wei KUO ,  Tsung-Hsien TSAI ,  Jia-Liang CHEN

    IPC分类号： H03H11/04 ,  H03H7/12

    CPC分类号： H03H11/12

    摘要： An RC filter is calibrated to a desired cutoff frequency by initializing the filter with a cutoff frequency. An input signal is filtered by the RC filter to provide a filter output signal having phase and frequency values. The cutoff frequency of the RC filter is adjusted based on the phase and frequency values of the filter output signal if the phase and frequency values do not satisfy a predetermined condition. The filtering and adjusting are repeated until the phase and frequency values of the filter output signal satisfy the predetermined condition. A calibration apparatus has a frequency generator, a resistor-capacitor (RC) filter, a phase comparator, a frequency detector, and a state machine. The phase comparator, frequency detector, and state machine are configured to calibrate the RC filter to a cutoff frequency specified by the reference signal based on a filter output signal of the RC filter.

    摘要翻译： 通过用截止频率初始化滤波器，将RC滤波器校准为所需的截止频率。 输入信号由RC滤波器滤波，以提供具有相位和频率值的滤波器输出信号。 如果相位和频率值不满足预定条件，则根据滤波器输出信号的相位和频率值来调整RC滤波器的截止频率。 重复滤波和调整直到滤波器输出信号的相位和频率值满足预定条件。 校准装置具有频率发生器，电阻 - 电容（RC）滤波器，相位比较器，频率检测器和状态机。 相位比较器，频率检测器和状态机被配置为基于RC滤波器的滤波器输出信号将RC滤波器校准到由参考信号指定的截止频率。

    METHOD AND SYSTEM FOR TIME TO DIGITAL CONVERSION WITH CALIBRATION AND CORRECTION LOOPS
    5.
    发明申请
    METHOD AND SYSTEM FOR TIME TO DIGITAL CONVERSION WITH CALIBRATION AND CORRECTION LOOPS 有权
    使用校准和校正灯进行数字转换的方法和系统

    公开(公告)号：US20120056769A1

    公开(公告)日：2012-03-08

    申请号：US12874462

    申请日：2010-09-02

    申请人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    发明人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    IPC分类号： H03M1/50

    CPC分类号： G04F10/005

    摘要： Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

    摘要翻译： 公开了时间到数字转换（TDC）的方法和装置。 定时电路包括TDC电路，校准模块和校正模块。 TDC电路被配置为提供指示周期性参考时钟信号的边沿与可变反馈信号之间的定时差的定时信号。 TDC电路还被配置为提供相对于参考时钟信号可变地延迟的延迟信号。 校准模块被配置为提供校准信号，以根据校准信号的时间延迟加上校正信号的时间延迟来增加和减少TDC电路的总延迟。 被配置为接收定时信号并提供校正信号的校正模块通过在参考时钟信号的频率下工作来最小化定时信号的频率响应中的谐波杂散。

    METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE
    6.
    发明申请
    METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE 有权
    用于放大时间差异的方法和装置

    公开(公告)号：US20110304372A1

    公开(公告)日：2011-12-15

    申请号：US12813620

    申请日：2010-06-11

    申请人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    发明人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    IPC分类号： H03H11/26

    CPC分类号： G04F10/005

    摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

    摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE
    7.
    发明申请
    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE 有权
    用于相位锁定环的自动频率校准及其使用方法

    公开(公告)号：US20130278303A1

    公开(公告)日：2013-10-24

    申请号：US13452138

    申请日：2012-04-20

    申请人： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    发明人： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC分类号： H03L7/08 ,  H03L7/00 ,  H03B19/00

    CPC分类号： H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    摘要： A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.

    摘要翻译： 锁相环包括被配置为接收参考频率和分频器频率并输出相位差信号的相位差检测器。 锁相环包括被配置为接收参考频率和相位差信号的码发生器，并输出粗调谐信号和复位信号。 锁相环包括配置为接收相位差信号并输出​​微调信号的数字环路滤波器。 锁相环包括配置成接收粗调和微调信号并输出​​输出频率的压控振荡器。 锁相环包括分配器，用于接收复位信号，分频器数控制信号和输出频率，并输出分频器。 锁相环包括被配置为接收除数比和复位信号的delta-sigma调制器，并输出分频数控制信号。

    PHASE FREQUENCY DETECTOR CIRCUIT
    9.
    发明申请
    PHASE FREQUENCY DETECTOR CIRCUIT 有权
    相位检测电路

    公开(公告)号：US20130135011A1

    公开(公告)日：2013-05-30

    申请号：US13308274

    申请日：2011-11-30

    申请人： Yen-Jen CHEN ,  I-Ting LEE ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    发明人： Yen-Jen CHEN ,  I-Ting LEE ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC分类号： H03D13/00 ,  H03L7/00

    CPC分类号： H03D13/00 ,  H03D13/004 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10

    摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

    摘要翻译： 相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。 边缘检测器电路被配置为接收第一输入信号和第二输入信号。 判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。 响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。